GoldMine: Automatic assertion generation using data mining and static analysis

Vasudevan, Sridhar R.; Sheridan,; Patel, M. S.; Tcheng,; Tuohy,; Johnson,

doi:10.1109/date.2010.5457129

Cited by 98 publications

(48 citation statements)

References 13 publications

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“…Additionally, the need for predefined checks is time consuming and error prone. The author in [10] proposes Goldmine tool which employ data mining algorithms and static analysis technologies to generate SVA from simulation traces and RTL design. Although numerous properties were generated with different levels of complexity, yet the results of the tool depend highly on the simulation cycles executed and the maturity of the RTL design.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

Kayed¹,

Abdelsalam²,

Guindi

2014

2014 15th International Microprocessor Test and Verification Workshop

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System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to find a simple way to capture design specifications from JEDEC standard and automatically generate SVA that can be used as checkers for DDR memory protocols. In this paper, we propose a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a Timing Diagram Markup Language (TDML) based format and generate SVA from the TDML document. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.

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Section: Related Workmentioning

confidence: 99%

A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

Kayed¹,

Abdelsalam²,

Guindi

2014

2014 15th International Microprocessor Test and Verification Workshop

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“…Following the successful paradigm of data mining algorithms in the verification domain [8], engineers are now turning their attention to that field as a means to address the verification pain of failure triage. The work in [6] is the first to determine failure relations through heuristic-based metrics that combine information from simulation and automated debugging.…”

Section: Introductionmentioning

confidence: 99%

Clustering-based failure triage for RTL regression debugging

Poulos

Veneris

2014

2014 International Test Conference

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Regression verification at the pre-silicon stage has experienced a dramatic boost in capabilities over the past years. With the aid of assertions, improved simulation coverage and formal verification tools, a vast amount of trace data and myriads of failures are often generated after each regression run. Along these lines, modern flows face an emerging need to appropriately categorize, prioritize and distribute these failures to the engineer(s) best-suited for detailed debugging of each failure. This task is known as failure triage. Despite its resource-intensive nature, triage remains a predominantly manual process. In this work, an automated data-mining failure triage framework is introduced that mines simulation and SAT-based design debugging data, uncovers relations among verification failures and automatically groups the related ones together. The core characteristic of the framework is a novel feature-based representation for verification failures and a new multiple-pass clustering strategy that surpass previous methodologies in accuracy, robustness and flexibility. The proposed triage engine achieves an 89% average accuracy in failure categorization and compared to existing solutions, it reduces the number of misplaced verification failures by 47% on the average.

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“…For example, consider the outgoing edges from ID in sion. GoldMine [20] uses static analysis on RTL design and a decision tree based supervised learning algorithm on simulation traces to generate assertions. Mandouh and Wassal [7] propose a framework that utilizes frequent and sequential pattern mining and known templates to extract RTL design properties.…”

Section: Pipeline Temporal Informationmentioning

confidence: 99%

Verifying micro-architecture simulators using event traces

Nyew

Onder

Önder

et al. 2014

Proceedings of the 28th ACM International Conference on Supercomputing

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Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere complexity of simulators makes using formal techniques difficult and calls for domain-specific knowledge to be a part of the verification process. This domain-specific information includes modeling the pipeline stages and the timing behavior of instructions with respect to these stages.We present an approach to simulator verification that uses domainspecific information to effectively capture a potential mismatch between the assumed architecture model and its simulator. We first discuss how a simulator-generated event trace can be fed into an automatically generated verification program from a first-order logic specification to verify that the simulator obeys the invariants. We then show techniques that extract simulator behavior from traces and present the results to the user in the form of graphs and rules. While the former seeks an assurance of implementation correctness by checking that the model invariants hold, the latter attempts to derive an extended model of the implementation and hence enables a deeper understanding of what was implemented.Our techniques are applicable to any micro-architecture simulator. We present the application of our techniques to hand-written simulators as well as to those generated from an architecture specification language.

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GoldMine: Automatic assertion generation using data mining and static analysis

Cited by 98 publications

References 13 publications

A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML

Clustering-based failure triage for RTL regression debugging

Verifying micro-architecture simulators using event traces

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