GPlace3.0

Abuowaimer, Ziad; Maarouf, Dani; Martin, Timothy J.; Foxcroft, Jérémy; Gréwal, Gary; Areibi, Shawki; Vannelli, A.

doi:10.1145/3233244

Cited by 48 publications

(5 citation statements)

References 20 publications

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“…For this FPGA implementation of MP-FAST, we used the Xilinx Alveo U280 card (Abuowaimer et al, 2018). While FPGAs are typically programmed with hardware description languages, Xilinx offers a 'high-level synthesis' tool, where algorithms can be written in C++ and then compiled into firmware.…”

Section: Figure 13mentioning

confidence: 99%

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Robust image descriptor for machine learning based data reduction in serial crystallography

Rahmani,

Nawaz,

Pennicard

et al. 2024

J Appl Crystallogr

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Serial crystallography experiments at synchrotron and X-ray free-electron laser (XFEL) sources are producing crystallographic data sets of ever-increasing volume. While these experiments have large data sets and high-frame-rate detectors (around 3520 frames per second), only a small percentage of the data are useful for downstream analysis. Thus, an efficient and real-time data classification pipeline is essential to differentiate reliably between useful and non-useful images, typically known as `hit' and `miss', respectively, and keep only hit images on disk for further analysis such as peak finding and indexing. While feature-point extraction is a key component of modern approaches to image classification, existing approaches require computationally expensive patch preprocessing to handle perspective distortion. This paper proposes a pipeline to categorize the data, consisting of a real-time feature extraction algorithm called modified and parallelized FAST (MP-FAST), an image descriptor and a machine learning classifier. For parallelizing the primary operations of the proposed pipeline, central processing units, graphics processing units and field-programmable gate arrays are implemented and their performances compared. Finally, MP-FAST-based image classification is evaluated using a multi-layer perceptron on various data sets, including both synthetic and experimental data. This approach demonstrates superior performance compared with other feature extractors and classifiers.

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Section: Figure 13mentioning

confidence: 99%

“…The different parts of the Xilinx UltraScale architecture. Used with permission of ACM, from Abuowaimer et al (2018).…”

Section: Figure 14mentioning

confidence: 99%

Robust image descriptor for machine learning based data reduction in serial crystallography

Rahmani,

Nawaz,

Pennicard

et al. 2024

J Appl Crystallogr

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“…Illustration of the internal architecture of a Xilinx UltraScale FPGA. The FPGA consists of an array of blocks such as I/O (input and output), Combinatorial Logic Blocks, Digital Signal Processing and memory in the form of SRAM, which can be flexibly configured [62].…”

Section: Data Transfer and Processing Chains In Detectorsmentioning

confidence: 99%

Data reduction and processing for photon science detectors

Pennicard,

Rahmani,

Graafsma

2024

Front. Phys.

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New detectors in photon science experiments produce rapidly-growing volumes of data. For detector developers, this poses two challenges; firstly, raw data streams from detectors must be converted to meaningful images at ever-higher rates, and secondly, there is an increasing need for data reduction relatively early in the data processing chain. An overview of data correction and reduction is presented, with an emphasis on how different data reduction methods apply to different experiments in photon science. These methods can be implemented in different hardware (e.g., CPU, GPU or FPGA) and in different stages of a detector’s data acquisition chain; the strengths and weaknesses of these different approaches are discussed.

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“…Detailed placement further improves the quality of the solution. During global placement, analytical placement performs well, such as Gplace [6] and UTPlaceF [7]. To further optimize FPGA placement results, analytical placers usually require a detailed placement step.…”

Section: Related Workmentioning

confidence: 99%

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Yu,

Guo

2023

Electronics

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The simulated annealing algorithm is an extensively utilized heuristic method for heterogeneous FPGA placement. As the application of neural network models on FPGAs proliferates, new challenges emerge for the traditional simulated annealing algorithm in terms of timing. These challenges stem from large circuit sizes and high heterogeneity in the block proportions typical in neural networks. To address these challenges, this study introduces a timing-driven simulated annealing placement algorithm. This algorithm integrates cluster criticality identification during the cluster selection phase, which enhances the probability of high-criticality cluster selection. In the cluster movement phase, the proposed method employs an improved weighted center movement for high-criticality clusters and a random movement strategy for other clusters. Experimental evidence demonstrates that the proposed placement algorithm decreases the average wire length by 1.52% and the average critical path delay by 5.03%. This improvement in performance is achieved with a marginal increase of 5.01% in runtime, as compared to VTR8.0.

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GPlace3.0

Cited by 48 publications

References 20 publications

Robust image descriptor for machine learning based data reduction in serial crystallography

Robust image descriptor for machine learning based data reduction in serial crystallography

Data reduction and processing for photon science detectors

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

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