Gpnocsim - A General Purpose Simulator for Network-On-Chip

This paper proposes an approach to the synthesis and modeling of networks-on-chip (NoCs) by using the NoCSimp library based on a simplified wormhole router with central buffer and without virtual channels. The analysis of the results of simulation and synthesis of NoCs with regular and quasi-optimal topologies with number of nodes 8 and 9 is given. It is shown that in the case where the number of NoC nodes is not a power of 2 the use of quasi-optimal topologies offers a significant advantage.

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“…Another high-level universal software simulator in Java is gpNoCsim. Its description and simulation results are given in [13].…”

Section: Comparison Of Nocsimp With Other Noc Modelsmentioning

confidence: 99%

Simulation and synthesis of networks-on-chip by using NoCSimp HDL library

Romanov

Ivannikov

Romanova³

2016

2016 IEEE 36th International Conference on Electronics and Nanotechnology (ELNANO)

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“…High level simulation [2], [4], [1] can be used in the early stages of development process for a faster, however less accurate, design space exploration. Usually those simulations are written in high level languages like C, C++ and Java.…”

Section: Introductionmentioning

confidence: 99%

“…The platform synthesis time is an obstacle, because any change in the target NoC demands the platform re-synthesis. Some approaches [4], [15] use the partial reconfiguration capabilities of state of art FPGAs to bypass this situation. Another drawback is the FPGA resources limitations which determine the maximum NoC size that can be emulated.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of SNMP-like protocol to manage a NoC emulation platform

Lima

Fresse

Rousseau

2014

2014 International Conference on Field-Programmable Technology (FPT)

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The Networks-on-Chip (NoCs) are currently the most appropriate communication structure for many-core embedded systems. An FPGA-based emulation platform can drastically reduce the time needed to evaluate a NoC, even if it is composed by tens or hundreds of distributed components. These components should be timely managed in order to execute an evaluation traffic scenario. There is a lack of standard protocols to drive FPGAbased NoC emulators. Such protocols could ease the integration of emulation components developed by different designers.In this paper, we evaluate a light version of SNMP (Simple Network Management Protocol) to manage an FPGA-based NoC emulation platform. The SNMP protocol and its related components are adapted to a hardware implementation. This facilitates the configuration of the emulation nodes without FPGA-resynthesis, as well as the extraction of emulation results. Some experiments highlight that this protocol is quite simple to implement and very efficient for a light resources overhead.

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“…For the purposes of this work and for the NoC case study scenario, gpNoCsim simulator is used. This simulator uses an adaptive routing algorithm based on XY algorithm with a modified turn model with virtual channel support and 4-stage pipelined router operation [23,24]. It also supports 64-bit flit width with worm-whole flow control, 2 virtual channels per link with buffer depth of 5 flits per virtual channel, and different traffic models.…”

Section: Topology Exploration Setup: Adaptability In Variousmentioning

confidence: 99%

“…This framework is built upon the object oriented modular design of the NoC architecture components [23].…”

Section: Topology Exploration: Ann Scalabilitymentioning

confidence: 99%

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

Savva

Theocharides

Nicopoulos

2017

Journal of Electrical and Computer Engineering

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This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96-99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.

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Gpnocsim - A General Purpose Simulator for Network-On-Chip

Cited by 31 publications

References 4 publications

Simulation and synthesis of networks-on-chip by using NoCSimp HDL library

Simulation and synthesis of networks-on-chip by using NoCSimp HDL library

Evaluation of SNMP-like protocol to manage a NoC emulation platform

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

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