GPU-Based, LDPC Decoding for 5G and Beyond

Abstract

In 5G New Radio (NR), low-density parity-check (LDPC) codes are included as the error correction codes (ECC) for the data channel. While LDPC codes enable a low, near Shannon capacity, bit error rate (BER), they also become a computational bottleneck in the physical layer processing. Moreover, 5G LDPC has new challenges not seen in previous LDPC implementations, such as Wi-Fi. The LDPC specification in 5G includes many reconfigurations to support a variety of rates, block sizes, and use cases. 5G also creates targets for supporting high-throughput and low-latency applications. For this new, flexible standard, traditional hardware-based solutions in FGPA and ASIC may struggle to support all cases and may be cost-prohibitive at scale. Software solutions can trivially support all possible reconfigurations but struggle with performance. This article demonstrates the high-throughput and low-latency capabilities of graphics processing units (GPUs) for LDPC decoding as an alternative to FPGA and ASIC decoders, effectively providing the high performance needed while maintaining the benefits of a software-based solution. In particular, we highlight how by varying the parallelization strategy for mapping GPU kernels to blocks, we can use the many GPU cores to compute one codeword quickly to target low-latency, or we can use the cores to work on many codewords simultaneously to target high throughput applications. This flexibility is particularly useful for virtualized radio access networks (vRAN), a next-generation technology that is expected to become more prominent in the coming years. In vRAN, the hardware computational resources will become decoupled from the specific computational functions in the RAN through virtualization, allowing for benefits such as load-balancing, improved scalability, and reduced costs. To highlight and investigate how the GPU can accelerate tasks such as LDPC decoding when containerizing vRAN functionality, we integrate our decoder into the Open Air Interface (OAI) NR software stack. With our GPU-based decoder, we measure a best case-latency of 87 μs and a best-case throughput of nearly 4 Gbps using the Titan RTX GPU.

Software-Defined GPU-CPU Empowered Efficient Wireless Federated Learning With Embedding Communication Coding for Beyond 5G

“…Jonathan Ling studied GPU as a digital signal processing accelerator for cloud RAN [39], which improves the throughput of data and accelerates the decoding process of LDPC. Chance Tarver works by changing the parallelization strategy of mapping GPU cores to blocks, using many GPU cores to quickly compute a codeword for low latency, or using cores to process multiple codewords simultaneously for targeted highthroughput applications [40]. The above researches are based on GPU hardware optimization to speed up the encoding and decoding process.…”

Efficient LDPC Encoder Design for IoT-Type Devices

“…While numerous hardware implementations of modern ECC codecs, including LDPC codecs, have already been developed, typically they are devoted to high-throughput demanding communication standards; thus, they are based on high-volume custom ICs [8][9][10], FPGAs [11][12][13][14], or GPU devices [15,16]. On the other hand, the typical physical-layer protocol stack for an IoT-type device is developed with low memory, device complexity and processing time requirements as the most important goals.…”

Multi-Gbps LDPC Decoder on GPU Devices

“…To improve the intra-codeword parallelism, the design must be effectively mapping the decoding algorithm to GPU devices. In our design, we extend the architecture described in [25] and divide the decoding progress into six parts: (1) Initialization and ordering, (2) check node update, (3) variable node update, (4) hard decision, (5) evaluate check (optional), and (6) bit packed and reordering. Each part corresponds to one CUDA kernel (in CUDA terminology, a kernel denotes an enclosed function).…”

“…GPU-based high-throughput LDPC decoders have been widely studied in the past years [21][22][23][24][25][26]. In [21], a high-throughput decoder based on layered scheduling was proposed.…”

“…The shortening and puncturing techniques in 5G NR were adopted in [24] when designing the LDPC decoder. To meet the different demands of 5G NR, [25] proposed an LDPC decoder with various working modes. The authors of [26] proposed a low-latency decoder design strategy that exploits additional parallelism, which also has a high throughput performance.…”