Graded Crystalline HfO₂ Gate Dielectric Layer for High-k/Ge MOS Gate Stack

Lee, Chan Ho; Yang, Jeong Yong; Heo, Junseok; Yoo, Geonwook

doi:10.1109/jeds.2021.3058631

Cited by 7 publications

(4 citation statements)

References 39 publications

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“…The V BI (−0.26 V) was calculated from the 1/C 2 curve (Figure S4a, Supporting Information), while the interface trap density (10 14 cm −2 eV −1 ) was estimated from the variablefrequency C-V characterization (Figure S4b, Supporting Information), which is higher compared to SiO 2 /Si interface. [47][48][49][50] This can be attributed to a large lattice mismatch between the Si and HfO 2 , generating the abundance of uncompensated dangling bonds at the HfO 2 /Si interface during the growth of the HfO 2 layer. They can also act as charge pockets for the photogenerated charge carriers inside the Si depletion region.…”

Section: Resultsmentioning

confidence: 99%

Electric‐Dipole Gated Two Terminal Phototransistor for Charge‐Coupled Device

Imran

Zhu

Sulaman

et al. 2023

Advanced Optical Materials

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The demand for charge‐coupled device (CCD) imagers has surged exponentially during the last decade owing to their exceptionally high quality and low noise imaging. However, they are still confronting the performance constraints of high operation power, low speed, and limited charge integration. Here, the electric‐dipole gated phototransistor operation without external gate bias is reported by using high‐k HfO2 dielectric material. The electrostatic coupling of photogenerated charges from the Si with the graphene channel through a 10 nm HfO2 layer is demonstrated. The device exhibits remarkable performance in the broadband spectrum (266–1342 nm) at low drain bias voltage. The high values of responsivity, external quantum efficiency, and detectivity of 3.7 × 103 A W−1, 0.72 × 104, and 6.20 × 1013 cmHz½ W−1, respectively, for 800 nm wavelength and 3.3 × 103 A W−1, 1.31 × 104, and 5.61 × 1013 cmHz½ W−1, respectively, for 400 nm wavelength without gate are achieved. This discovery may potentially eliminate the requirement for gate terminals from commercial CCD devices. The power efficient features of this gateless image sensor can be fabricated at the industrial scale for the future machine vision market.

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Section: Resultsmentioning

confidence: 99%

Electric‐Dipole Gated Two Terminal Phototransistor for Charge‐Coupled Device

Imran

Zhu

Sulaman

et al. 2023

Advanced Optical Materials

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“…As a result, the temperature had to be raised above normal ohmic contact annealing temperature (850 • C). To minimize the gate leakage through the grain boundary between the crystallized HfO 2 , a 30 nm thick amorphous HfO 2 dielectric layer was deposited under the same ALD condition [15,16]. Finally, Ni/Au (20/50 nm) contact was formed on the gate dielectric.…”

Section: Methodsmentioning

confidence: 99%

Low Subthreshold Slope AlGaN/GaN MOS-HEMT with Spike-Annealed HfO2 Gate Dielectric

et al. 2021

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AlGaN/GaN metal-oxide semiconductor high electron mobility transistors (MOS-HEMTs) with undoped ferroelectric HfO2 have been investigated. Annealing is often a critical step for improving the quality of as-deposited amorphous gate oxides. Thermal treatment of HfO2 gate dielectric, however, is known to degrade the oxide/nitride interface due to the formation of Ga-containing oxide. In this work, the undoped HfO2 gate dielectric was spike-annealed at 600 °C after the film was deposited by atomic layer deposition to improve the ferroelectricity without degrading the interface. As a result, the subthreshold slope of AlGaN/GaN MOS-HEMTs close to 60 mV/dec and on/off ratio>109 were achieved. These results suggest optimizing the HfO2/nitride interface can be a critical step towards a low-loss high-power switching device.

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“…In this regard, strained silicon, III-V materials, and germanium (Ge) are suggested as the future channel material as these provide higher electron mobility compared to silicon. [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] Out of these non-silicon materials, Ge graves the highest attention of device researchers due to its exceptionally high hole mobility. [17][18][19][20][21] As the current technology deals with CMOS architecture, we need both NMOS and PMOS to be implemented.…”

mentioning

confidence: 99%

“…[17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] Out of these non-silicon materials, Ge graves the highest attention of device researchers due to its exceptionally high hole mobility. [17][18][19][20][21] As the current technology deals with CMOS architecture, we need both NMOS and PMOS to be implemented. Also, a comparable performance between NMOS and PMOS devices is necessary for the precise operation of circuits.…”

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confidence: 99%

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

Barman

Baishya

2022

ECS J. Solid State Sci. Technol.

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This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) field-effect transistor in terms of two device material variations (silicon/Si and germanium/Ge) with the aid of 3-D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (Ion) by 30.28, 30.29, 29.91, and 26.98 µA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases Ion more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

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Graded Crystalline HfO₂ Gate Dielectric Layer for High-k/Ge MOS Gate Stack

Cited by 7 publications

References 39 publications

Electric‐Dipole Gated Two Terminal Phototransistor for Charge‐Coupled Device

Electric‐Dipole Gated Two Terminal Phototransistor for Charge‐Coupled Device

Low Subthreshold Slope AlGaN/GaN MOS-HEMT with Spike-Annealed HfO2 Gate Dielectric

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

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