Graphene Field-Effect Transistor Model With Improved Carrier Mobility Analysis

Tian, Jing; Katsounaros, Anestis; Smith, D.W.G.; Hao, Yang

doi:10.1109/ted.2015.2469109

Cited by 48 publications

(11 citation statements)

References 31 publications

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“…dn is the charge carrier concentration due to potential fluctuations (puddles) created by impurities in the oxide and the substrate close to the graphene interface. 16,[25][26][27] We take n th into account by the sum of n e þ n h at the Dirac point in Eq. (8).…”

Section: A115-5 Bonmann Et Al: Effect Of Oxide Traps On Channel Trmentioning

confidence: 99%

“…In the capacitance model of GFETs the contribution of the interface capacitance, C int , is often neglected in the expression for the total capacitance, C t . 10,16 In the present study, we propose a semiempirical model for the dependency of oxide charges and charge carriers in a) Electronic mail: marbonm@chalmers.se graphene on the applied gate voltage, including interface states. The model allows us to investigate their effect on resistance and capacitance characteristics and the extracted mobility values.…”

Section: Introductionmentioning

confidence: 99%

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Effect of oxide traps on channel transport characteristics in graphene field effect transistors

Bonmann

Vorobiev

Stake

et al. 2017

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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A semiempirical model describing the influence of interface states on characteristics of gate capacitance and drain resistance versus gate voltage of top gated graphene field effect transistors is presented. By fitting our model to measurements of capacitance–voltage characteristics and relating the applied gate voltage to the Fermi level position, the interface state density is found. Knowing the interface state density allows us to fit our model to measured drain resistance–gate voltage characteristics. The extracted values of mobility and residual charge carrier concentration are compared with corresponding results from a commonly accepted model which neglects the effect of interface states. The authors show that mobility and residual charge carrier concentration differ significantly, if interface states are neglected. Furthermore, our approach allows us to investigate in detail how uncertainties in material parameters like the Fermi velocity and contact resistance influence the extracted values of interface state density, mobility, and residual charge carrier concentration.

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Section: A115-5 Bonmann Et Al: Effect Of Oxide Traps On Channel Trmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effect of oxide traps on channel transport characteristics in graphene field effect transistors

Bonmann

Vorobiev

Stake

et al. 2017

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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show abstract

“…The gate region of QDGFET is comprised of this insulating layer and QD layers, whereas in a conventional MOSFET only gate oxide layer (insulator) is present in the gate region. [11][12][13][14][15][16]. The device structure of a QDGFET is shown in Fig.…”

Section: Quantum Dot Gate Field-effect Transistormentioning

confidence: 99%

“…However, the problem of the RTD and RTT is the ON/OFF ratio and the process compatibility with the existing silicon process. Recently, carbon nanotube FET [10][11][12], graphene FET [13][14][15] are also showing promising results. However, the main problem of these devices is that they are basically binary devices having tunable threshold voltages.…”

Section: Introductionmentioning

confidence: 99%

Three‐state dynamic random‐access memory (DRAM)

Karmakar

2020

IET Circuits, Devices & Systems

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This work shows the design of three-valued dynamic random-access memory (DRAM) cell using quantum dot gate field effect transistor. DRAM is very popular for increasing device integration in integrated circuits. Storing multiple numbers of bits in a single DRAM cell increases the device integration further. The process technology is compatible with the conventional silicon process. The various write and read operations of the three-value DRAM cell are also discussed in this work. 4 Fabrication The QDGFET can be fabricated using conventional Si process technology. In this process, the cleaned Silicon wafer is used as a starting material for the device. The 1200 Å thick silicon dioxide

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“…Different devices are in the research phase to implement multi-valued logic in future. Among them resonant tunnelling diode (RTD) [4,5], resonant tunnelling transistor (RTT) [6,7], carbon nanotube FET (CNTFET) [8,9], graphene FET [10][11][12], and quantum dot gate FETs (QDGFETs) are promising. This group has already successfully demonstrated different FETs like QDGFET [13,14], spatial wave-function switched FETs (SWSFET) [15,16], quantum dot gate-quantum dot channel FET (QDG-QDCFET) [17] in multi-valued logic application.…”

Section: Introductionmentioning

confidence: 99%

Generation of four states in MOSFET for future multivalued logic circuit design

Karmakar

2019

IET Circuits, Devices & Systems

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Analogue Quaternary logic is very promising logic for multi-valued logic implementation. Four states can be generated in different ways. This paper shows the generation of four states in two different semiconductor MOSFETs by modifying their gate structure as well as channel structure. In three well-spatial wave-function switched FET (SWSFET), the four states are generated by connecting their drain terminals. On the other hand, in the quantum dot gate-spatial wave-function switched FET (QDG-SWSFET), the four states are generated by the combining effects of SWSFET and QDGFET.

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Graphene Field-Effect Transistor Model With Improved Carrier Mobility Analysis

Cited by 48 publications

References 31 publications

Effect of oxide traps on channel transport characteristics in graphene field effect transistors

Effect of oxide traps on channel transport characteristics in graphene field effect transistors

Three‐state dynamic random‐access memory (DRAM)

Generation of four states in MOSFET for future multivalued logic circuit design

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