GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

Nai, Lifeng; Hadidi, Ramyad; Sim, Jaewoong; Kim, Hyojong; Kumar, Pranith

doi:10.1109/hpca.2017.54

Cited by 222 publications

(175 citation statements)

References 36 publications

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“…Some work [8], [14] uses novel processing-in-memory (PIM) technology [15] to offload the atomic operations to specialized memory region, which reduces the processing time of atomic operations. However, it needs to incorporate with specialized memory architecture and also increases the memory requests since all atomic operations needs to be sent to the memory.…”

Section: B Inefficiency In Graph Processingmentioning

confidence: 99%

An efficient graph accelerator with parallel data conflict management

Yao

Zheng

Jin

et al. 2018

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques

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Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential in essential when some vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. This is particularly true for processing natural graphs.In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank and WCC) are typically incremental and simplex. This hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect a novel graphspecific accelerator that can simultaneously process atomic vertex updates for massive parallelism on the conflicting data access while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protection for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx Virtex UltraScale+ XCVU9P with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with single-chip version).Input: Graph G = (V , E), root vertex r Output: Distance of each ∈ V , dis[ ] 1 Q ← r ; 2 dis[r ] = 0; 3 while Q is not empty do 4

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Section: B Inefficiency In Graph Processingmentioning

confidence: 99%

An efficient graph accelerator with parallel data conflict management

Yao

Zheng

Jin

et al. 2018

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques

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“…This paper studies the default address mapping of HMC. 5 In a higher level of abstraction, a 4 KB OS page is allocated in two banks across all vaults (HMC 1.1), 6 promoting memory level parallelism for reading/writing the contents of a page. When we access multiple pages allocated serially in the physical address space, as the number of concurrent accesses to these pages increases, bank-level parallelism (BLP) increases as well.…”

Section: Hmc Memory Addressingmentioning

confidence: 99%

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

Hadidi

Asgari

Mudassar

et al. 2017

2017 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally associated with memories. A practical 3D-stacked memory is Hybrid Memory Cube (HMC), which provides significant access bandwidth and low power consumption in a small area. Although several studies have taken advantage of the novel architecture of HMC, its characteristics in terms of latency and bandwidth or their correlation with temperature and power consumption have not been fully explored. This paper is the first, to the best of our knowledge, to characterize the thermal behavior of HMC in a real environment using the AC-510 accelerator and to identify temperature as a new limitation for this state-ofthe-art design space. Moreover, besides bandwidth studies, we deconstruct factors that contribute to latency and reveal their sources for high-and low-load accesses. The results of this paper demonstrates essential behaviors and performance bottlenecks for future explorations of packet-switched and 3D-stacked memories.

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“…Majority of the NMC proposals are targeted towards different types of data processing applications e.g. graph processing [29], [38], [53], MapReduce [34], [37], [44], machine learning [55], [56], database search [32], [35], [39], [47], [49], [51]. The logic layer connected to the memory via silicon vias in 3D stacked memories is considered to be the most important play ground of innovation [4], [29], [30], [37], [38], [40], [41], [45], [46], [48], [50], [52], [55]- [57] but the efficacy of those new innovations has only been tested using simulators.…”

Section: Discussionmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

Cited by 222 publications

References 36 publications

An efficient graph accelerator with parallel data conflict management

An efficient graph accelerator with parallel data conflict management

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube

Near-memory computing: Past, present, and future

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