Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Abstract-In this paper, a new open-loop architecture with good dynamic performance and strong harmonic rejection capability is proposed for single-phase grid synchronization under distorted conditions. Different from previous single-phase grid synchronization algorithms based on the phase locked loop (PLL) technique, the proposed method is to estimate the frequency and phase angle of the grid voltage in an open-loop manner so that fast dynamic response and enhanced system stability can be achieved. Firstly, an open-loop frequency estimation algorithm is introduced under ideal grid condition. Then, it is extended to distorted grid voltages through the combination of the developed frequency estimation unit and a pre-filtering stage consisting of a second-order lowpass filter and a cascaded delayed signal cancellation (DSC) module. In addition, a transient process smoothing (TPS) unit is designed to achieve smooth frequency transients in cases where the grid voltage experiences fast and large changes. The working principle of the new frequency estimation algorithm and the developed single-phase grid synchronization approach is given in detail, together with some simulation and experiment results for verifying their performance.