Ground bounce in digital VLSI circuits

Abstract

Abstract-This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

“…Of course, insertion of the right amount of decoupling capacitors at the right places in the supply distribution network can help alleviate the inductive voltage drop effects [52].…”

A 7V-to-30V-Supply 190A/µs Regulated Gate Driver in a 5V CMOS-Compatible Process

“…c. Significant power loss in shoot-through current: During switching of the inverter chain, there is a shoot-through current flowing from the V reg node to ground. Such dynamic current causes the V reg voltage to drop (Heydari & Pedram, 2003). Since the operating voltage is 30V, the power of the shoot-through current still contributes much to the power loss.…”

Charge Recycling in Power-Gated CMOS Circuits

“…Since the charger-recycling transistor is usually much smaller than the sleep transistors, the leakage-increase ratio given in (20) is usually too small when compared to the power saving achieved by using the charge-recycling technique.…”

“…The sleep transistor is turned on at t=0 when the initial voltage of C G is V 0 , i.e., V G (t=0)=V 0 . Based on the results of [20], the positive peak of the GB occurs during the time when S N operates in the saturation region. If we neglect the channel length modulation effect, the saturation current of S N does not depend on V 0 .…”