Ground temporal logic: A logic for hardware verification

Cyrluk, David; Narendran, Paliath

doi:10.1007/3-540-58179-0_59

Cited by 23 publications

(19 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This example originated with the first work on symbolic model checking [7], and has subsequently become a standard for verification research [10,13]. In our version, we make use of both stalling and forwarding to resolve read-after-write hazards in the pipeline.…”

Section: Resultsmentioning

confidence: 99%

Convergence Testing in Term-Level Bounded Model Checking

Bryant

Lahiri

Seshia

2003

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. We consider the problem of bounded model checking of systems expressed in a decidable fragment of first-order logic. While model checking is not guaranteed to terminate for an arbitrary system, it converges for many practical examples, including pipelined processors. We give a new formal definition of convergence that generalizes previously stated criteria. We also give a sound semi-decision procedure to check this criterion based on a translation to quantified separation logic. Preliminary results on simple pipeline processor models are presented.

show abstract

Section: Resultsmentioning

confidence: 99%

Convergence Testing in Term-Level Bounded Model Checking

Bryant

Lahiri

Seshia

2003

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…Cyrluka nd Narendran [ 6] definedafirst-order temporal logic-ground temporall ogic (GTL), whichf or universallyq uantified computation paths, falls in between first-order and propositional temporal logics. GTL models consist of first-order languagei nterpretationm odels and infinite sequences of states.…”

Section: R Elated Workmentioning

confidence: 99%

“…Fort his decidable fragment,t hey did nots howh ow to build the decision procedure, though. Compared to [6], our L MDG * is more expressive (cf. Section 4).…”

Section: R Elated Workmentioning

confidence: 99%

See 1 more Smart Citation

First-Order LTL Model Checking Using MDGs

Wang¹,

Tahar²,

Mohamed³

2004

Automated Technology for Verification and Analysis

View full text Add to dashboard Cite

Abstract. In this paper, we describeafi rst-order linear time temporal logic (LTL) model checkerb ased on multiway decision graphs (MDG). We developed afi rst-order temporal language, L MDG * ,w hiche xpresses asubset of many-sorted first-order LTLand extends an earlier language, L MDG ,d efined for an MDG based abstractC TL model checking. We derived as et of rules, enabling the transformation of L MDG * formulas into generalized Büchi automata( GBA). The product of this GBA and the abstracts tate machine (ASM) model is checkedf or language emptiness. We have lifted two instances of the generalized Strongly Connected Component(SCC)-hull (GSH)c hecking algorithm [17] to support abstractd ata and uninterpreted functions based on operators available in the MDG package. Experimental results have shown the superiority of our tool compared to the same instances of GSH implemented with BDDs in VIS. 1I ntroductionFormalv erificationh as receivedc onsiderable attention fromt he electricale ngineering,c omputers cience and the industryc ommunities, where many BDD based formal verification tools being developed overt he years. These, however, suffer fromt he well-known state space explosion problem. Multiway Decision Graphs (MDGs) [5] have been introduced as one way to reduce this problem. MDGsa re basedo namany-sorted first-order logic with ad istinction between concrete and abstract sorts. Abstract variablesa re usedt or epresentd ata signals,whileuninterpreted functionsymbols are used to representdata operations, providing amorecompact description of circuits with complex data path. Many MDG basedverificationapplicationshave been developed duringthe last decade, including invariant checking, sequential equivalence checking, and abstract CTL model checking [21]o fa bstract state machines( ASM) [ 5]. TheM DG tools are available at [22].In this paper we introduce an ew MDG verification application by implementing automata based model checking of as ubseto ffi rst-order lineart ime temporal logic (LTL). Generally,L TL model checking verifiesaKripkestructure with respect to ap ropositional linear time temporal logic (PLTL) formula. A PLTL formula φ is valid if it is satisfied by all paths of theK ripkes tructure M .T he validation of φ can be done by converting itsn egation into aG eneralizedBu chiA utomaton( GBA) [ 19] B ¬ φ ,c omposing the automaton with the

show abstract

“…See [11,24] for details. If the abstraction mapping is given this way, then once the proof is split according to the definition of hum_cycles, the resulting statement of correctness is usually an instance of a decidable fragment of the theory Ground Temporal Logic (GTL2) [10].…”

Section: A Proof Strategy For Microprocessor Correctnessmentioning

confidence: 99%