Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping

Li, J.Z.; Bai, J.; Hydrick, J. M.; Park, J.S.; Major, Cheryl; Carroll, M.; Fiorenza, J.G.; Lochtefeld, A.

doi:10.1016/j.jcrysgro.2009.03.018

Cited by 16 publications

(10 citation statements)

References 13 publications

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“…The intermediate peak, centered at $1.498 eV (with small variations for the different sizes) may be assigned to a free electronneutral acceptor transition (e-C 0 , 1.494 eV) due to carbon impurities incorporated during the MOVPE growth. 15 These two lines are present also in the GaAs control epitaxy grown on a semi-insulating GaAs substrate. Finally, the lowest energy optical transition at 1.484 eV coincides with the main line collected from GaAs layers on planar substrates.…”

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confidence: 88%

“…13 A similar mechanism coined aspect ratio trapping prevails when GaAs and GaAs/Ge are grown into submicron sized openings of dielectric masks. [14][15][16] Even vertical dislocations perpendicular to the substrate surface are expelled from finite-sized crystals by interacting with slanting facets. 17,18 The recently reported method of three-dimensional (3D) heteroepitaxy, providing space filling arrays of tall, relaxed Ge crystals on patterned Si(001) substrates, may emerge as a promising solution also for the integration of GaAs on Si.…”

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confidence: 99%

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Strain relaxation of GaAs/Ge crystals on patterned Si substrates

Taboada

Kreiliger

Falub

et al. 2014

Applied Physics Letters

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We report on the mask-less integration of GaAs crystals several microns in size on patterned Si substrates by metal organic vapor phase epitaxy. The lattice parameter mismatch is bridged by first growing 2-μm-tall intermediate Ge mesas on 8-μm-tall Si pillars by low-energy plasma enhanced chemical vapor deposition. We investigate the morphological evolution of the GaAs crystals towards full pyramids exhibiting energetically stable {111} facets with decreasing Si pillar size. The release of the strain induced by the mismatch of thermal expansion coefficients in the GaAs crystals has been studied by X-ray diffraction and photoluminescence measurements. The strain release mechanism is discussed within the framework of linear elasticity theory by Finite Element Method simulations, based on realistic geometries extracted from scanning electron microscopy images.

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confidence: 88%

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confidence: 99%

Strain relaxation of GaAs/Ge crystals on patterned Si substrates

Taboada

Kreiliger

Falub

et al. 2014

Applied Physics Letters

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“…Therefore, TDD and APB are further reduced by introducing a buffer layer. Li et al [ 124 ] investigated the growth of GaAs layers on polished Ge/Si by selective ART. They first grew the Ge layer on the patterned SiO 2 substrate, then deposited GaAs on the SEG Ge buffer layer.…”

Section: Latest Approach Of Heteroepitaxy Of Si-based Iii-v Group Mat...mentioning

confidence: 99%

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Wang

et al. 2022

Nanomaterials

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Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized

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“…Based on ART and CMP, a high-quality Ge crystal can be obtained on Si substrate. Thanks to the similar lattice coefficients (αGe = 5.658Å, αGaAs = 5.653Å), a low dislocation density GaAs layer can then be prepared on the Ge/Si substrate [ 326 ].…”

Section: Iii-v Materialsmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping

Cited by 16 publications

References 13 publications

Strain relaxation of GaAs/Ge crystals on patterned Si substrates

Strain relaxation of GaAs/Ge crystals on patterned Si substrates

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

State of the Art and Future Perspectives in Advanced CMOS Technology

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