High quality InP thin films have been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping (ART), whereby defects arising from lattice mismatch (~8%) are trapped by laterally confining sidewalls. Double-buffer layers and two-step ART growth processes have been employed to trap vertical threading dislocations originating at InP/Si interface. InP film quality and optical properties have been analyzed using SEM, TEM and room temperature photoluminescence. Full trapping of dislocations has been demonstrated for trenches up to 400 nm in width without the additional formation of defects at the sidewalls above 500 nm initial growth. This approach shows great promise for the integration of III-V materials onto silicon.

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO 2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO 2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al 2 O 3 as the gate oxide. The 10 m gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ϳ500 cm 2 / Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

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This paper describes the recent development of the Aspect Ratio Trapping (ART) heterointegration technique. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 micron wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.