(Invited) Aspect Ratio Trapping: A Unique Technology for Integrating Ge and III-Vs with Silicon CMOS

Abstract

This paper describes the recent development of the Aspect Ratio Trapping (ART) heterointegration technique. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 micron wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

“…Yet large-area planar thin ilms are more amenable in some device applications [135]. Towards this goal, III-V materials are epitaxially grown out of closely spaced trenches and continued laterally on top of the oxide stripes until materials from adjacent trenches merge together.…”

“…CMP is generally required to establish a lat surface for device integration [137,138]. Despite various process modiications, reducing the coalescence dislocations remains an unsolved challenge [135]. An improved method to grow coalesced GaAs thin ilms on patterned Si was demonstrated recently to produce GaAs-on-V-grooved Si (GoVS) templates [139].…”

Hetero-epitaxy of high quality germanium film on silicon substrate for optoelectronic integrated circuit applications

“…Another similar technique is called aspect ratio trapping. 59 Mesas with smaller dimension of ,1 lm and higher aspect ratio of .2 are patterned on the SiO 2 layer and are etched to reach the Si surface. Ge epilayers are subsequently grown selectively on the patterned windows.…”

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

“…Although the ART technique discussed above can effectively solve the APB problem, and block the propagation of crystalline defects using the groove mask, this technique also limits the maximum achievable dimension of III-V epitaxial layers, which are more amenable in some device applications [ 142 ]. In order to provide a large film plane for the preparation of III−V devices, the ART technique needs to be continuously optimized so that the SEG III−V materials are epitaxial and grown out of closely spaced trenches, and extend laterally above the oxidation strips until the materials from adjacent grooves merge together to form a continuous high quality epitaxial layer.…”