Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks

Garros, X.; Cassé, M.; Reimbold, G.; Martín, F.; Leroux, C.; Fanton, Aurélien; Renault, O.; Cosnier, V.; Boulanger, F.

doi:10.1109/vlsit.2008.4588567

Cited by 29 publications

(20 citation statements)

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“…Nevertheless, Al 2 O 3 below HfO 2 shows slightly higher mobility at low field, while Al 2 O 3 above HfO 2 shows slightly higher mobility at high field. This does not show a correlation with the defect density measured with LF noise and CP current, however, a correlation is observed with NBTI [10] as will be discussed later in this paper. …”

Section: B Electrical Performancementioning

confidence: 58%

Impact of Al<inf>2</inf>O<inf>3</inf> position on performances and reliability in high-k metal gated DRAM periphery transistors

Aoulaiche

Simoen

Ritzenthaler

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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The impact of the Al 2 O 3 position with respect to HfO 2 in the process flow, is investigated. It is shown that Al 2 O 3 incorporation in order to increase the pMOS threshold voltage, slightly degrades the mobility, slightly increases NBTI and increases the EOT with respect to the reference without Al 2 O 3 . Moreover, the trap density profiles depend on the Al 2 O 3 position: higher in the interfacial layer when Al 2 O 3 is below and higher in the HfO 2 when Al 2 O 3 is above HfO 2 . Furthermore, Al 2 O 3 below HfO 2 shows higher gate leakage, reduced LF noise but marginal NBTI difference compared to AL 2 O 3 above HfO 2 .

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Section: B Electrical Performancementioning

confidence: 58%

Impact of Al<inf>2</inf>O<inf>3</inf> position on performances and reliability in high-k metal gated DRAM periphery transistors

Aoulaiche

Simoen

Ritzenthaler

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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“…In the case of the samples without SAFII, the highest ΔV th degradation was observed at 12% nitrogen concentration. Garros et al [8] reported that nitrogen diffuses into either the bulk high-k dielectric or is incorporated at the high-k/Si interface during metal-nitride-gate deposition. The accumulation of nitrogen at the high-k/Si interface enhances the NBTI.…”

Section: Methodsmentioning

confidence: 99%

Effects of a HfMoN Metal Gate and Self-Aligned Fluorine-Ion Implantation on the Negative-Bias Temperature Instability of pMOSFETs With $\hbox{Gd}_{2} \hbox{O}_{3}$ Gate Dielectrics

Wang

Peng

Lai

et al. 2011

IEEE Electron Device Lett.

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The effects of self-aligned fluorine-ion implantation on the negative-bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors with HfMoN metal gates and Gd 2 O 3 gate dielectrics were investigated. The threshold voltage V th can be adjusted from −0.8 to −0.02 V by increasing the nitrogen concentration in the HfMoN metal gates. However, this adjustment degrades the NBTI, and consequently, the V th shifts are increased by 140 and 500 mV for samples with low (0%) and high (12%) nitrogen concentration, respectively, in the HfMoN metal gates. This degradation of NBTI was improved by fluorine incorporation.Index Terms-Fluorine, high-k, metal gate, negative-bias temperature instability (NBTI), nitrogen.

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“…Two scenarios with various mean traps Nt IL and Nt HK are considered. The single layer DCM fits the MC distributions but with effective parameters Nt ox and η ox related to the true trap parameters by (12) and (13).…”

Section: B Poisson Distribution Of the Trap Number: Ntmentioning

confidence: 99%

“…Considering (12), it is therefore possible to estimate the error made using Nt ox for evaluating the average total number of traps in the bilayer gate-stack rigorously given by Nt IL + Nt HK . This is done in Fig.…”

Section: B Poisson Distribution Of the Trap Number: Ntmentioning

confidence: 99%

“…However, the error becomes maximum for a ratio equal to Nt HK /Nt IL ∼ 3.8 corresponding to a preferential trapping in the HK layer. This means that, under NBTI stress, known to degrade preferentially the IL [12], the error remains limited. This can explain why this model is successfully used so far to characterize the NBTI-induced variability.…”

Section: B Poisson Distribution Of the Trap Number: Ntmentioning

confidence: 99%

See 1 more Smart Citation

Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide

Subirats

Garros

Husseini

et al. 2015

IEEE Trans. Electron Devices

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In this paper, we revisit the classic single layer defect centric model (DCM), largely used in reliability studies, in the more realistic case of bilayer gate oxide transistors integrating an interface layer and a high-K dielectric. The Monte Carlo method and 3-D electrostatic simulations are used to determine the impact of the traps present in both layers on the V t of transistors. It is proved that the DCM is able to capture the trap-induced variability of bilayer transistors but with effective model parameters, which have no more a true physical meaning as in the case of the single layer gate oxide. An extended DCM, accounting for a two trap distributions, is then proposed to better explain the degradation measured on bilayer transistors. Finally, this extended DCM finds another application in the evaluation of the bias temperature instability-induced variability of static RAM cells.

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Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks

Cited by 29 publications

References 0 publications

Impact of Al<inf>2</inf>O<inf>3</inf> position on performances and reliability in high-k metal gated DRAM periphery transistors

Impact of Al<inf>2</inf>O<inf>3</inf> position on performances and reliability in high-k metal gated DRAM periphery transistors

Effects of a HfMoN Metal Gate and Self-Aligned Fluorine-Ion Implantation on the Negative-Bias Temperature Instability of pMOSFETs With $\hbox{Gd}_{2} \hbox{O}_{3}$ Gate Dielectrics

Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide

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