H.264/AVC interpolation optimization

Abstract

This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.

Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW–SIMD DSP

“…The horizontal and vertical filtering with dot product instructions can generate eight samples at each iteration, and achieve the iteration interval of 8 cycles and 11 cycles, respectively. Although the use of dot product instructions seems less efficient than using shift and addition instructions [22,23], the dotproduct implementation shows better performances, 3.7 times faster for the horizontal filtering and 6.1 times faster for the vertical filtering because it utilizes the hardware multipliers.…”