Half pitch 14 nm direct pattering with Nanoimprint lithography

Nakasugi, Tetsuro; Kono, Takuya; Fukuhara, Kazuya; Hatano, Masayuki; Tokue, Hiroshi; Komori, Mika; Tsuda, Hitoshi; Komukai, Toshihiko; Takahata, Kazuo; Katō, Hirokazu; Kobayashi, Katsutoshi; Mitra, Arindam; Kobayashi, Sachiko; Inoue, Soichi; Higashiki, Tatsuhiko; Motokawa, Takeharu; Saito, Masato; Kanamitsu, Shingo; Itoh, Masamitsu; Imamura, Takahiro; Matasunaga, K.; Hashimoto, Kohji; Kim, Y.; Cho, J.; Jung, Wanyeong

doi:10.1109/iedm.2018.8614578

Cited by 11 publications

(5 citation statements)

References 3 publications

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“…In 2018, Nakasugi presented CDU results of 0.4nm on 14nm half pitch line/space patterns, with a line width roughness of 2.7nm. 19 The imprint process is just the start however, and it is critical to be able to successfully etch the underlying materials. For NIL this means that we need to address both the NIL resist etch durability and make sure that the etching of the underlying residual layer is not a problem.…”

Section: B Cdu Managementmentioning

confidence: 99%

Optimization of NIL and associated pattern transfer processes for the fabrication of advanced devices

Ogusu,

Tamura,

Nomura

et al. 2024

Novel Patterning Technologies 2024

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Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity.Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications.Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In 2018, Hiura et al. reported a mix and match overlay (MMO) of 3.4 nm and a single machine overlay (SMO) across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool. These results were achieved by combining a magnification actuator system with a High Order Distortion Correction (HODC) system, thereby enabling correction of high order distortion terms up to K30.Unlike other lithographic methods, NIL provides the pattern flexibility and a cost structure to address a much larger application space. Potential market expansion and includes high end semiconductor devices, CMOS image sensors, optical couplers for augmented reality headsets and meta optical elements (MOEs). The purpose of this paper is to describe the patterning and pattern transfer performance enhancements to enable improved edge placement error for DRAM applications, allow the patterning of dual damascene back end structures with a simpler single step imprint patterning process and to create working MOEs operational in the visible spectrum.

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Section: B Cdu Managementmentioning

confidence: 99%

Optimization of NIL and associated pattern transfer processes for the fabrication of advanced devices

Ogusu,

Tamura,

Nomura

et al. 2024

Novel Patterning Technologies 2024

View full text Add to dashboard Cite

show abstract

“…In 2018, Nakasugi presented CDU results of 0.4nm on 14nm half pitch line/space patterns, with a line width roughness of 2.7nm. 18 The imprint process is just the start however, and it is critical to be able to successfully etch the underlying materials. For NIL this means that we need to address both the NIL resist etch durability and make sure that the etching of the underlying residual layer is not a problem.…”

Section: Cdu Managementmentioning

confidence: 99%

Nanoimprint post processing techniques to address edge placement error

Ogusu

Ishida

Tamura

et al. 2023

Novel Patterning Technologies 2023

View full text Add to dashboard Cite

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices. In addition, we present a reverse tone pattern transfer process that has the potential to further reduce GCDU and EPE for NIL.

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“…NIL is also attracting attention as a green lithography technology because it requires much lower power consumption than other lithographic techniques and it does not require chemical developing solutions because it does not involve development processes 6,7 . Application of NIL to NAND flash memory fabrication is currently under consideration and the development of the required fabrication techniques is progressing for memory patterns with a minimum half-pitch (HP) of 14 nm, e.g., memory cells and contact holes 8 . NIL is also expected to be applied as a back-end-of-line (BEOL) lithography technique for fabrication of logic integrated circuits (ICs) 9 .…”

Section: Introductionmentioning

confidence: 99%

Open/short-TEG evaluation of 24nm-half-pitch-W damascene interconnects based on nanoimprint lithography

Suzuki,

Ueda,

Hiroshima

et al. 2024

Novel Patterning Technologies 2024

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Nanoimprint lithography (NIL) is regarded as a promising technique for application to fabrication of the dual damascene structures that are commonly fabricated in back-end-of-line layers. Initial development work has commenced with a simple single-level process to evaluate the suitability of NIL for back-end processing applications. In this work, a test pattern with a minimum half-pitch of 24 nm was patterned using NIL, and W damascene interconnects were then fabricated via a combination of W deposition followed by chemical mechanical polishing. The electrical performances of the test devices were subsequently evaluated using the open/short test element group. The line resistances and leakage currents of the W interconnect structures fabricated using NIL showed good cumulative distributions at the designed minimum linewidth of 24 nm. We also demonstrated that a diagonal zigzag capacitor pattern with a pattern size of 2X nm showed good electrical properties.

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Half pitch 14 nm direct pattering with Nanoimprint lithography

Cited by 11 publications

References 3 publications

Optimization of NIL and associated pattern transfer processes for the fabrication of advanced devices

Optimization of NIL and associated pattern transfer processes for the fabrication of advanced devices

Nanoimprint post processing techniques to address edge placement error

Open/short-TEG evaluation of 24nm-half-pitch-W damascene interconnects based on nanoimprint lithography

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