Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed. C 2011 Society of Photo-Optical Instrumentation Engineers (SPIE).

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

Nanoimprint lithography is one of the candidates for NGL. Recently, the "S-FIL TM" (Step and Flash Imprint Lithography) has been developed by MII (Molecular Imprints, Inc.). Accordingly, it is necessary to build next-generation devices and study unit processes without delay. Because of good resolution, CD uniformity and LER, nanoimprint lithography is attractive. However, nanoimprint lithography (S-FIL) involves risks. In order to judge whether the S-FIL is applicable to the study of unit processes and test device fabrication, we had studied the feasibility of S-FIL technology.As a result of previous work, we obtained the results of basic evaluation and confirmed the applicability of nanoimprint lithography for unit process study and basic test device fabrication.However, application of nanoimprint lithography to various test devices requires the template resolution of 22nmHP, OL accuracy on multilayer resist, and defect density for various patterns. Therefore, in order to judge whether the S-FIL application is extendable to various test devices, we studied the characteristics of S-FIL.As a result of this work, we confirmed that the nanoimprint application is extendable to fabrication of various test devices. And as a result of basic evaluation, improvement of template resolution is confirmed and the value of 22nmHP is obtained. We confirmed the robustness of the alignment process. The defect density is related in pattern density and spread time. Thus, reduced DD without throughput loss is required.

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