Halo-Doped Hetero Dielectric Nanowire MOSFET Scaled to the Sub-10 nm Node

Kumar, Pankaj; Balaji, B.; Rao, K. Srinivasa

doi:10.1007/s42341-023-00448-6

Cited by 8 publications

(6 citation statements)

References 36 publications

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“…This shows the on-state behavior of the TFET as shown in Figure 2. A high Ion/Ioff ratio indicates better switching behavior and power efficiency of the proposed device (25,26). The proposed tunneling device, the tunneling current should be a dominant factor.…”

Section: Resultsmentioning

confidence: 97%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

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Section: Resultsmentioning

confidence: 97%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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“…The 10-nanometer node allows for more transistors per unit area and can offer improved performance and power efficiency. The overlap can impact the device's characteristics, such as threshold voltage and subthreshold swing, which are crucial for TFET performance (22). In this device, electrons tunnel through a thin insulating barrier between the source and the channel, which is different from traditional transistors like MOSFETs, where electrons move through a conductive channel as shown in Figure 1.…”

Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node

Howldar,

Balaji,

Srinivasa Rao

2024

IJE

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“…Therefore, the proposed device design of DMG-FinFET with high-K dielectric materials, engineers can create transistors that offer improved qualitative performance, reduced power consumption, and enhanced reliability for advanced semiconductor technologies (25,26). High-K dielectric materials and the FinFET architecture help achieve lower subthreshold slopes, reducing power consumption in subthreshold slop operation (27). This is particularly advantageous for applications requiring energy-efficient operation in low-power states.…”

Section: Figure 1 Proposed Dmg-finfetmentioning

confidence: 99%

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Padmaja,

Vemana Chary,

Erigela

et al. 2024

IJE

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A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate -FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2. The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

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Halo-Doped Hetero Dielectric Nanowire MOSFET Scaled to the Sub-10 nm Node

Cited by 8 publications

References 36 publications

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

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