Halo profile engineering to reduce Vt fluctuation in high-k/metal-gate nMOSFET

Wy, Chen; Yu, Tianjun; Ohtou, Tetsu; Sheu, Y-M; Wu, Jun; C, Liu

doi:10.1109/sispad.2010.5604546

Cited by 1 publication

(2 citation statements)

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“…[5] In this work, pocket Carbon (C),Nitrogen (N) co-implantation in NMOSFET have been shown to suppress Boron (B) diffusion in silicon with pre-amorphization implant (PAI) [6]. Moreover, reducing pocket tilt angle is also discussed to improve the threshold voltage mismatch caused by discrete random dopant fluctuation (RDF) [3].…”

Section: Introductionmentioning

confidence: 99%

“…For example, the threshold voltage variation (σVt) is known to be limited by short-channel effect (SCE), line edge roughness (LER),gate electrode work-function (WF) variation, discrete random dopant fluctuation (RDF) and metallurgical junction front edge roughness(FER). The impact of threshold voltage variation on digital and analogue circuits becomes extremely important [1,2,3,4]. This local variation is known as mismatch.…”

Section: Introductionmentioning

confidence: 99%

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40nm Low Power MOSFET Transistor VT Fluctuation Control

Li¹,

Lin²,

Huang³

et al. 2012

ECS Trans.

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This paper presents an approach to reduce threshold voltage (VT) fluctuation in 40nm low power MOSFET transistor. Introducing nitrogen (N) co-implantation in pocket architecture and reducing pocket implant tilt angle are two factors known for decreasing the VT fluctuation (σVt). In this paper, we combined these two VT fluctuation reduction approaches in source and drain extension (SDE) process and demonstrated that it could not only improve VT mismatch (σVt) ~30%, but also reduce MOSFET overlay capacitance ~ 8%.

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Section: Introductionmentioning

confidence: 99%