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This paper presents an approach to reduce threshold voltage (VT) fluctuation in 40nm low power MOSFET transistor. Introducing nitrogen (N) co-implantation in pocket architecture and reducing pocket implant tilt angle are two factors known for decreasing the VT fluctuation (σVt). In this paper, we combined these two VT fluctuation reduction approaches in source and drain extension (SDE) process and demonstrated that it could not only improve VT mismatch (σVt) ~30%, but also reduce MOSFET overlay capacitance ~ 8%.