Hamiltonian cycle embedding for fault tolerance in balanced hypercubes

Hao, Rong‐Xia; Zhang, Ru; Feng, Yan-Quan; Zhou, Jin‐Xin

doi:10.1016/j.amc.2014.07.015

Cited by 38 publications

(15 citation statements)

References 24 publications

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“…Cheng and Hao studied the embedding of various cycles in faulty balanced hypercubes. Hao et al studied the fault‐tolerant embedding of Hamiltonian cycles into balanced hypercubes. Lv et al studied the fault‐tolerant embedding of Hamiltonian cycles and paths in

Q_{n}^{k}

‐cubes with considering structure faults.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

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Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

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Q_{n}^{k}

‐cubes with considering structure faults.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

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“…Cheng et al [3] proved that BH n is (n − 1)-vertex-fault-tolerant edge-bipancyclic. Hao et al [6] showed that there is a fault-free Hamiltonian path between any two adjacent vertices in BH n with 2n − 2 faulty edges. Cheng et al [5] proved that BH n is 2n − 3 edge-fault-tolerant 6-edge-bipancyclic for all n ≥ 2.…”

Section: Introductionmentioning

confidence: 99%

Fault-Free Hamiltonian Cycles in Balanced Hypercubes with Conditional Edge Faults

2019

Int. J. Found. Comput. Sci.

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The balanced hypercube, BH n , is a variant of hypercube Q n . Zhou et al. [Inform. Sci. 300 (2015) 20-27] proposed an interesting problem that whether there is a fault-free Hamiltonian cycle in BH n with each vertex incident to at least two fault-free edges. In this paper, we consider this problem and show that each fault-free edge lies on a fault-free Hamiltonian cycle in BH n after no more than 4n − 5 faulty edges occur if each vertex is incident with at least two fault-free edges for all n ≥ 2. Our result is optimal with respect to the maximum number of tolerated edge faults.

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“…A particular property of the balanced hypercube is that each processor has a backup processor that shares the same neighborhood. For more results about the balanced hypercubes, please refer to [4], [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

Constructing Two Completely Independent Spanning Trees in Balanced Hypercubes

Yang

Pai

Chang

et al. 2019

IEICE Trans. Inf. & Syst.

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A set of spanning trees of a graphs G are called completely independent spanning trees (CISTs for short) if for every pair of vertices x, y ∈ V(G), the paths joining x and y in any two trees have neither vertex nor edge in common, except x and y. Constructing CISTs has applications on interconnection networks such as fault-tolerant routing and secure message transmission. In this paper, we investigate the problem of constructing two CISTs in the balanced hypercube BH n , which is a hypercube-variant network and is superior to hypercube due to having a smaller diameter. As a result, the diameter of CISTs we constructed equals to 9 for BH 2 and 6n − 2 for BH n when n 3. key words: interconnection networks, completely independent spanning trees, balanced hypercubes, diameter

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Hamiltonian cycle embedding for fault tolerance in balanced hypercubes

Cited by 38 publications

References 24 publications

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fault-Free Hamiltonian Cycles in Balanced Hypercubes with Conditional Edge Faults

Constructing Two Completely Independent Spanning Trees in Balanced Hypercubes

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