Hardware-accelerated dynamic binary translation

Abstract

Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms. In this work, we propose a hardware accelerated Dynamic Binary Translation where the first steps of the DBT process are fully accelerated in hardware. Results shows that using our hardware accelerators leads to a speed-up of 8× and a cost in energy 18× lower, compared with an equivalent software approach.

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

“…There are minor per-approach variations to these segments, for instance, maximum size (e.g., number of instructions) of the segment [19,77], presence of instructions unsupported by the accelerator [17,79], total number of inputs/outputs into the sequence [13,68], the type of stride [58] in the case of loops, or support for conditional execution, i.e., multiple paths [67].…”

“…Binary Translation -Segment Type A1, Detection B2, [77]. During the initial stages of execution, a first-pass binary translation implemented in hardware retargets the code, and also instruments it for segment detection in a second phase.…”

“…Second, a small number of approaches [59,77] rely on specializing a generic processor architecture rather than interfacing an existing host processor with additional hardware. Approaches where a tightly coupled accelerator is controlled by custom instructions are similar to this method.…”

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation

“…To our knowledge, little academic work has been done on the topic, and the only open VLIW-DBT tool we are aware of is Hybrid-DBT 2 . Hybrid-DBT is an open-source DBT framework operating on the RISC-V host ISA and targeting VLIW architectures [6]. In this work, we built on this framework to handle and exploit a Runtime Reconfigurable VLIWswhich is described in the next subsection.…”

“…Hybrid-DBT framework, on which we based our work, is a hardware accelerated DBT framework [6]. Three different accelerators have been designed: an instruction translator reduces the overhead of cold-code execution; a hardware instruction scheduler reduces the cost of continuous optimization as the scheduling step becomes cheap.…”