Hardware Acceleration of Explainable Machine Learning

Abstract

Machine learning (ML) is successful in achieving human-level artificial intelligence in various fields. However, it lacks the ability to explain an outcome due to its blackbox nature. While recent efforts on explainable AI (XAI) has received significant attention, most of the existing solutions are not applicable in real-time systems since they map interpretability as an optimization problem, which leads to numerous iterations of time-consuming complex computations. Although there are existing hardware-based acceleration framework for XAI, they are implemented through FPGA and designed for specific tasks, leading to expensive cost and lack of flexibility. In this paper, we propose a simple yet efficient framework to accelerate various XAI algorithms with existing hardware accelerators. Specifically, this paper makes three important contributions. (1) The proposed method is the first attempt in exploring the effectiveness of Tensor Processing Unit (TPU) to accelerate XAI. (2) Our proposed solution explores the close relationship between several existing XAI algorithms with matrix computations, and exploits the synergy between convolution and Fourier transform, which takes full advantage of TPU's inherent ability in accelerating matrix computations. (3) Our proposed approach can lead to realtime outcome interpretation. Extensive experimental evaluation demonstrates that proposed approach deployed on TPU can provide drastic improvement in interpretation time (39x on average) as well as energy efficiency (69x on average) compared to existing acceleration techniques.

Quantum-Based Molecular Dynamics Simulations Using Tensor Cores

“…It was the careful reformulation and combination of methods presented in this paper that was necessary to achieve the demonstrated level of performance. Indeed, even as hardware becomes more efficient and higher performing, we expect the same basic advantage to hold: low-precision arithmetics on specialized hardware, such as tensor cores and tensor processing units, , or field-programmable gate arrays and neuromorphic processors, − will be substantially faster than higher precision arithmetics on those same architectures. In this way, our results present a general road map for higher-performance QMD simulations also using future accelerated hardware.…”

“…In this article, we explore how tensor cores can be used as an effective tool to accelerate QMD simulations. Tensor cores, and the closely related tensor processing units, − are a new form of hardware designed for calculations involving deep neural networks in machine learning applications and provide an extraordinary amount of computational speed and energy efficiency . However, peak performance is limited to tensor contractions, i.e., matrix–matrix multiplications, using only low, mixed-precision floating-point operations.…”

Intra-class deep learning object detection on embedded computer system

“…The original image dataset is scaled down again using the operator-supervised bicubic method. The operator is used here, assuming the operator is a perfect AI engine compared to the distance-median algorithm to check the image quality of down-scaling [22]- [25]. Figure 3 shows the research design of the Plumeria L classification.…”

Fast training of a transformer for global multi-horizon time series forecasting on tensor processing units

“…Since its public release, TPU accelerators have been applied to various research topics that demand very high processing and memory capabilities. Examples of those domains are DNN training subject to large batch sizes and specialized learning rate algorithms [17], [18], distributed evolution strategies for meta-learning [19], acceleration of explainable machine learning [20], and simulation of quantum physics [21], to mention a few. Regarding the transformer, NLP and CV projects constitute the majority of TPU-assisted research using this architecture, partially due to the high availability of pre-trained models and TPU-ready software implementations.…”