Hardware and software architectures for the CELL processor

Day, M. N.; Hofstee, Peter

doi:10.1145/1084834.1084837

Cited by 8 publications

(5 citation statements)

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“…The design style of Systems-on-a-Chip (SoCs) has its origins in application specific integrated circuits (ASICs) and embedded system design, which tends to focus on the synthesis of a system for a given application (or set of applications). By contrast, SCHMs such as the Hyperprocessor, (14) the Cell, (15,16) and the Sandblaster (17) are more general hardware solutions, which focus on more general forms of programmability at the system (chip) level. Each has initially focused on a class of applications.…”

Section: Motivationmentioning

confidence: 99%

Amdahl’s Law Revisited for Single Chip Systems

Paul

Meyer

2007

Int J Parallel Prog

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Amdahl's Law is based upon two assumptions -that of boundlessness and homogeneity -and so it can fail when applied to single chip heterogeneous multiprocessor designs, and even microarchitecture. We show that a performance increase in one part of the system can negatively impact the overall performance of the system, in direct contradiction to the way Amdahl's Law is instructed. Fundamental assumptions that are consistent with Amdahl's Law are a heavily ingrained part of our computing design culture, for research as well as design. This paper points in a new direction. We motivate that emphasis should be made on holistic, system level views instead of divide and conquer approaches. This, in turn, has relevance to the potential impacts of custom processors, system-level scheduling strategies and the way systems are partitioned. We realize that Amdahl's Law is one of the few, fundamental laws of computing. However, its very power is in its simplicity, and if that simplicity is carried over to future systems, we believe that it will impede the potential of future computing systems.

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Section: Motivationmentioning

confidence: 99%

Amdahl’s Law Revisited for Single Chip Systems

Paul

Meyer

2007

Int J Parallel Prog

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“…Unlike the majority of the proposed solutions in this space, we target off-the-shelf processors rather than processors with novel hardware mechanisms (ideal target woulds be the Hydra [10] or Cell [11] processors). Other researchers have come up with some highly interesting new hardware designs to support implicit medium-grained parallelism.…”

Section: Mid-level Parallelismmentioning

confidence: 99%

“…A typical scenario will involve an n-way SMT processor on an m-way CMP with possibly multiple chips on a single platform; or even a chip containing heterogeneous processing elements, such as the Cell processor [11]. On such a platform, the optimal mapping of parallelized tasks from an application (these may be successive loop iterations, partitioned loops, or recursive procedure calls) to processing elements may change significantly with program inputs; different regions of an application may also require different mappings.…”

Section: Introductionmentioning

confidence: 99%

Dynamic parallelization and mapping of binary executables on hierarchical platforms

Yardimci

Franz

2006

Proceedings of the 3rd Conference on Computing Frontiers

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As performance improvements are being increasingly sought via coarse-grained parallelism, established expectations of continued sequential performance increases are not being met. Current trends in computing point towards platforms seeking performance improvements through various degrees of parallelism, with coarse-grained parallelism features becoming commonplace in even entry-level systems.Yet the broad variety of multiprocessor configurations that will be available that differ in the number of processing elements will make it difficult to statically create a single parallel version of a program that performs well on the whole range of such hardware. As a result, there will soon be a vast number of multiprocessor systems that are significantly under-utilized for lack of software that harnesses their power effectively. This problem is exacerbated by the growing inventory of legacy programs in binary executable form with possibly unreachable source code. We present a system that improves the performance of optimized sequential binaries through dynamic recompilation. Leveraging observations made at runtime, a thin software layer recompiles executing code compiled for a uniprocessor and generates parallelized and/or vectorized code segments that exploit available parallel resources. Among the techniques employed are control speculation, loop distribution across several threads, and automatic parallelization of recursive routines.Our solution is entirely software-based and can be ported to existing hardware platforms that have parallel processing capabilities. Our performance results are obtained on real hardware without using simulation.In preliminary benchmarks on only modestly parallel (2-way) hardware, our system already provides speedups of upto 40% on SpecCPU benchmarks, and near-optimal speedups on more obviously parallelizable benchmarks.

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“…Due to the embarrassingly parallel structure of most MapReduce applications, MapReduce can also take advantage of processors that expose large amounts of data parallelism via wide SIMD units or multithreading, as well as the ample on-chip bandwidth available on these processors. MapReduce ports on the Cell [12], GPUs [13] and Larrabee [14], exhibit the aforementioned architectural strengths.…”

Section: Introductionmentioning

confidence: 99%

Rearchitecting MapReduce for Heterogeneous Multicore Processors with Explicitly Managed Memories

Papagiannis

Nikolopoulos

2010

2010 39th International Conference on Parallel Processing

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Abstract-This paper presents a new design and an implementation of the runtime system of MapReduce for heterogeneous multicore processors with explicitly managed local memories. We advance the state of the art in runtime support for MapReduce using five instruments: (1) A new multi-threaded, event-driven controller for task instantiation, task scheduling, synchronization, and bulk-synchronous execution of MapReduce stages. The controller improves utilization of controlefficient cores, minimizes control overhead in the runtime system, and overlaps task instantiation with task scheduling on compute-efficient cores. (2) An implicit partitioning scheme which eliminates redundant memory copies. (3) An adaptive memory management scheme which combines efficient memory preallocation for applications with statically known output volume with dynamic allocation using runahead tasks for applications with statically unknown output volume. (4) An optimized quick-sort/merge-sort scheme which reduces the critical path length of merge-sort. (5) An optimized execution scheme which avoids redundant data transfers to and from local stores in applications that emit keys with the same value. Put together, these techniques accelerate representative MapReduce workloads by a factor of 1.81× (geometric mean) compared to a reference design that represents the state of the art.

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Hardware and software architectures for the CELL processor

Cited by 8 publications

References 0 publications

Amdahl’s Law Revisited for Single Chip Systems

Amdahl’s Law Revisited for Single Chip Systems

Dynamic parallelization and mapping of binary executables on hierarchical platforms

Rearchitecting MapReduce for Heterogeneous Multicore Processors with Explicitly Managed Memories

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