2020
DOI: 10.1109/tmtt.2020.3005178
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Hardware and Software Solutions for Active Frequency Scalable (Sub)mm-Wave Load–Pull

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Cited by 12 publications
(3 citation statements)
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“…In the literature, fundamental load-pull has been demonstrated at > 135 GHz. These systems use up/down conversion techniques to extend the frequency range of conventional NVNA-based measurement systems of 67 GHz [8] [9]. Harmonic load-pull systems have been reported at mm-wave, these use load diplexers to perform active injection to harmonically tune load impedance.…”
Section: Introductionmentioning
confidence: 99%
“…In the literature, fundamental load-pull has been demonstrated at > 135 GHz. These systems use up/down conversion techniques to extend the frequency range of conventional NVNA-based measurement systems of 67 GHz [8] [9]. Harmonic load-pull systems have been reported at mm-wave, these use load diplexers to perform active injection to harmonically tune load impedance.…”
Section: Introductionmentioning
confidence: 99%
“…The characterization of DHBT variants under largesignal excitation (generally, via load-pull measurements) is then essential to accurately model transistor behavior in high-frequency PA circuit design. However, the literature provides relatively few reports of load-pull characterization at frequencies of 94 GHz and higher [5], [6], [7], [8]. While circuits are also desired at frequencies much above W-band, 94 GHz load-pull measurements provide an excellent opportunity to validate device models for PA design.…”
Section: Introductionmentioning
confidence: 99%
“…The proposed direct calibration/de-embedding technique (e.g., M1 direct calibration/de-embedding) has been employed to extract the intrinsic device parameters for model validation up to 220GHz [5]. In this contribution, we employ the above mentioned technique in conjunction with large signal device characterization, i.e., mm-wave constant wave (CW) load-pull [6] to extract the intrinsic device large signal metrics and compare them with foundry device models. In this work, the intrinsic device data is obtained employing 1 st tier on wafer calibration, in close proximity to the DUT, employing a fixture design as presented in [4], shown in a simplified 3D drawing in Fig.…”
Section: Introductionmentioning
confidence: 99%