Hardware and Software Task Scheduling for ARM-FPGA Platforms

Dorflinger, Alexander; Albers, Mark; Schlatow, Johannes; Fiethe, Björn; Michalik, H.; Keldenich, Phillip; Fekete, Sándor P.

doi:10.1109/ahs.2018.8541481

Cited by 10 publications

(6 citation statements)

References 10 publications

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“…This step generates solutions by exploring the design space through iterative assignement of the implementation variant, e.g. whether TMR is enabled or not, and mapping to execution resources in R. The performance is optimized by minimizing the makespan of the functional graph using an algorithm developed in [22]. Non-reasonable solutions of the full permutation of tasks for the given solution are rejected, leaving 128 candidates to be analyzed in the here discussed reliability prediction stage.…”

Section: Case-study and Discussionmentioning

confidence: 99%

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

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Dorflinger

Albers

et al. 2019

2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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We introduce a model-based reliability estimation to preserve application availability in CPU-FPGA systems exposed to soft errors under varying environment conditions. The estimation is used as an in-system method to select a suitable configuration for changing radiation conditions. This allows systems to autonomously adapt their configuration in order to balance between reliability and performance. Such a selfadaptation goes beyond the state-of-the-art, where adaptation relies on preplanned reactive mode changes. By autonomously evaluating new configurations, our self-adaptation process is capable of increasing the availability by selecting the configuration with the desired application reliabilities for the current environment conditions.

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Section: Case-study and Discussionmentioning

confidence: 99%

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

Mostl

Dorflinger

Albers

et al. 2019

2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

Self Cite

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“…Ref. [17] exploits A* search algorithm to place hardware tasks in the programmable logic at appropriate times. The model presented in this paper not only optimizes throughput but also takes power consumption as one of the optimization objectives, while it does not partition the area of the reconfiguration region.…”

Section: Related Workmentioning

confidence: 99%

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

et al. 2020

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Dynamically partially reconfigurable (DPR) technology based on FPGA is applied extensively in the field of high-performance computing (HPC) because of its advantages in processing efficiency and power consumption. To make full use of the advantages of DPR in execution efficiency, we build a DPR system model that meets to the actual application requirements and the objective constraints. According to the consistency of reconfiguration order and dependencies, we propose two algorithms based on simulated annealing (SA). The algorithms partition FPGA resource to several regions and schedule tasks to the regions. In order to improve the performance of the algorithms, we exploit the module merging technology to improve the parallelism of task execution and design a new solution generation method to speed up the convergence speed. Experimental results show that the proposed algorithms have a lower time complexity than mixed-integer linear programming (MILP), iterative scheduler (IS) and Ant Colony Optimization (ACO). For applications with more tasks, the proposed algorithms show performance advantages in producing better partitioning and scheduling results in a shorter time.

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“…Still, the high acceleration rates (e.g., the disp to pointcloud component executes 32 times faster in hardware than in software) compensate this drawback. More details on system reconfiguration and the DPR capability under Genode OS used in this demonstration are given in [2].…”

Section: Hardware Accelerationmentioning

confidence: 99%

Demonstrating Controlled Change for Autonomous Space Vehicles

Dorflinger

Albers

Fiethe

et al. 2019

2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Recent research discusses concepts of infield changes to overcome the drawbacks of conventional lab-based system design processes. In this paper, we evaluate the concept of controlled change by applying it to a demonstration of a potential future space exploration scenario with mobile robots. The robots are capable of executing several image computations for exploration, object detection and pose estimation, which can be allocated to both FPGA-and processor resources of a System-on-Chip. The demonstrator addresses three scenarios which cover application-, environment-, and platform change. The system adapts itself to any of the named changes. This capability can increase the autonomy of future space missions. Exemplary, the demonstrator executes adaption of applications during operation to fulfill the mission goals, adaption of reliability under changing environment conditions, and adaption to sensor failure.

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Hardware and Software Task Scheduling for ARM-FPGA Platforms

Cited by 10 publications

References 10 publications

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

Demonstrating Controlled Change for Autonomous Space Vehicles

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