Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

Malik, Aqsa; Thörnberg, Benny; Imran, Muhammad; Lawal, Najeem

doi:10.1155/2014/815378

Cited by 10 publications

(6 citation statements)

References 31 publications

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“…Such cases must be resolved at the end of the frame. Similarly, Thornberg and Lawal [ 20 ] and Malik et al [ 13 ] perform a simple Union and defer merger resolution until the end of the frame.…”

Section: Prior Workmentioning

confidence: 99%

Union-Retire: A New Paradigm for Single-Pass Connected Component Analysis

Bailey

Klaiber

2021

Communications in Computer and Information Science

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Most connected component labelling and analysis algorithms are based on some variant of Union-Find . In this paper, it is shown the Find operation is unnecessary for single-pass algorithms, leading to the Union-Retire approach where the focus is on connectivity rather than labelling. The computational complexity of the resulting algorithm is linear with the number of pixels within an image. It is shown that the resulting algorithm requires significantly less memory than existing algorithms, making it ideal for embedded image processing.

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Section: Prior Workmentioning

confidence: 99%

Union-Retire: A New Paradigm for Single-Pass Connected Component Analysis

Bailey

Klaiber

2021

Communications in Computer and Information Science

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“…Higher throughput rates are achieved with the techniques presented in References [26,27,28,29,30]. In References [27,28], run-length encoding techniques are exploited for labeling connected components while representing equivalences with linked lists.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

“…Therefore, the resolution of equivalences involves only pointer redirection operations and removes the chaining problem. The pipeline architecture proposed in Reference [29] removes the blanking period for label merging by dividing the operations into two stages, but it requires twice the memory resources.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Spagnolo

Perri

Corsonello

2019

Sensors

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Connected Component Analysis (CCA) plays an important role in several image analysis and pattern recognition algorithms. Being one of the most time-consuming tasks in such applications, specific hardware accelerator for the CCA are highly desirable. As its main characteristic, the design of such an accelerator must be able to complete a run-time process of the input image frame without suspending the input streaming data-flow, by using a reasonable amount of hardware resources. This paper presents a new approach that allows virtually any feature of interest to be extracted in a single-pass from the input image frames. The proposed method has been validated by a proper system hardware implemented in a complete heterogeneous design, within a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) System on Chip (SoC) device. For processing 640 × 480 input image resolution, only 760 LUTs and 787 FFs were required. Moreover, a frame-rate of ~325 fps and a throughput of 95.37 Mp/s were achieved. When compared to several recent competitors, the proposed design exhibits the most favorable performance-resources trade-off.

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“…The system can perform on-board radiometric correction, geometric correction, and texture extraction. Malik et al [25] built a quick process hardware platform using an FPGA. The hardware platform could process 390 frames of 640 × 480 images per second.…”

Section: Introductionmentioning

confidence: 99%

On-Board Ortho-Rectification for Images Based on an FPGA

et al. 2017

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Abstract:The traditional ortho-rectification technique for remotely sensed (RS) images, which is performed on the basis of a ground image processing platform, has been unable to meet timeliness or near timeliness requirements. To solve this problem, this paper presents research on an ortho-rectification technique based on a field programmable gate array (FPGA) platform that can be implemented on board spacecraft for (near) real-time processing. The proposed FPGA-based ortho-rectification method contains three modules, i.e., a memory module, a coordinate transformation module (including the transformation from geodetic coordinates to photo coordinates, and the transformation from photo coordinates to scanning coordinates), and an interpolation module. Two datasets, aerial images located in central Denver, Colorado, USA, and an aerial image from the example dataset of ERDAS IMAGINE 9.2, are used to validate the processing speed and accuracy. Compared to traditional ortho-rectification technology, the throughput from the proposed FPGA-based platform and the personal computer (PC)-based platform are 11,182.3 kilopixels per second and 2582.9 kilopixels per second, respectively. This means that the proposed FPGA-based platform is 4.3 times faster than the PC-based platform for processing the same RS images. In addition, the root-mean-square errors of the planimetric coordinates ϕ X and ϕ Y and the distance ϕ S are 1.09 m, 1.61 m, and 1.93 m, respectively, which can meet the requirements of correction accuracy in practice.

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Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

Cited by 10 publications

References 31 publications

Union-Retire: A New Paradigm for Single-Pass Connected Component Analysis

Union-Retire: A New Paradigm for Single-Pass Connected Component Analysis

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

On-Board Ortho-Rectification for Images Based on an FPGA

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