Hardware architecture of high-performance digital hologram generator on the basis of a pixel-by-pixel calculation scheme

Abstract

In this paper we propose a hardware architecture for high-speed computer-generated hologram generation that significantly reduces the number of memory access times to avoid the bottleneck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation, rather than light source-by-source calculation. The second is a parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last scheme is a fully pipelined calculation scheme and exactly structured timing scheduling, achieved by adjusting the hardware. The proposed hardware is structured to calculate a row of a computer-generated hologram in parallel and each hologram pixel in a row is calculated independently. It consists of and input interface, an initial parameter calculator, hologram pixel calculators, a line buffer, and a memory controller. The implemented hardware to calculate a row of a 1920×1080 computer-generated hologram in parallel uses 168,960 lookup tables, 153,944 registers, and 19,212 digital signal processing blocks in an Altera field programmable gate array environment. It can stably operate at 198 MHz. Because of three schemes, external memory bandwidth is reduced to approximately 1/20,000 of the previous ones at the same calculation speed.

Hardware implementations of computer-generated holography: a review

“…107 Seo et al proposed a hardware architecture based on pixel-by-pixel calculation scheme. 87,88,92,95 In this line of work, the authors efficiently reduced the number of memory accesses by utilizing the pixel-by-pixel method, which is different from the conventional light source-by-source calculation method. The authors also demonstrated a VLSI chip, based on the proposed FPGA architecture.…”

Design and Implementation of Digital Hologram Content Using Modified Depth Information

“…This section describes the CGH calculation method [2][3][4][5] and the method using a recursive addition system. The CGH generating equation is defined as Eq.…”

Interpolation-based Object Decomposition and Parallel Computation Method for Large-Scale Computer Generated Hologram

“…Seo et al also implemented FPGA boards for CGH computation. [19]. All the above parallel computation procedures used parallelism either in the hologram plane or in the object plane, but never both.…”