Hardware Architecture of Improved Tomlinson-Harashima Precoding for Downlink MC-CDMA

Lin, Kuang-Hao; Lin, Hsin-Lei; Chang, Robert Chen-Hao; Wu, Ching-Fen

doi:10.1109/apccas.2006.342357

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…In spite of the high volume of research work published around the topic of precoding algorithms, the issues raised by their implementation have not been given the same attention. Some of the few publications on this area, such as [10][11][12], describe precoding systems that either have a considerable complexity in terms of allocated hardware resources or provide a rather low data transmission rate.…”

Section: Introductionmentioning

confidence: 99%

Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding

Barrenechea

Mendicute²,

Arruti³

2013

International Journal of Reconfigurable Computing

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The nonlinear vector precoding (VP) technique has been proven to achieve close-to-capacity performance in multiuser multiple-input multiple-output (MIMO) downlink channels. The performance benefit with respect to its linear counterparts stems from the incorporation of a perturbation signal that reduces the power of the precoded signal. The computation of this perturbation element, which is known to belong in the class of NP-hard problems, is the main aspect that hinders the hardware implementation of VP systems. To this respect, several tree-search algorithms have been proposed for the closest-point lattice search problem in VP systems hitherto. Nevertheless, the optimality of these algorithms has been assessed mainly in terms of error-rate performance and computational complexity, leaving the hardware cost of their implementation an open issue. The parallel data-processing capabilities of field-programmable gate arrays (FPGA) and the loopless nature of the proposed tree-search algorithms have enabled an efficient hardware implementation of a VP system that provides a very high data-processing throughput.

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Section: Introductionmentioning

confidence: 99%

Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding

Barrenechea

Mendicute²,

Arruti³

2013

International Journal of Reconfigurable Computing

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“…The LQD unit executes the Gram-Schmidt algorithm in Eqs. (5) and (6) with floating-point arithmetic operation because the matrix decomposition requires high accuracy and large dynamic range computations. The IC unit performs the inference cancellation in Eq.…”

Section: Overall Structurementioning

confidence: 99%

“…Hardware architectures of THP have been presented by Lin et al [5] and Gu and Parhi [6]. Their architectures focus on single-input and single-output (SISO) systems.…”

Section: Introductionmentioning

confidence: 99%

A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

Shimazaki

Yoshizawa

Hatakawa

et al. 2013

IEICE Trans. Fundamentals

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SUMMARYThis paper presents a VLSI design of a TomlinsonHarashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.

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