Hardware architecture specification and constraint-based WCET computation

Abstract

The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times.

Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages

“…Computing WCETs is commonly done through measurement [28] or static analyses with, e.g., OTAWA [29]. Measurement approaches often lead to under-estimating WCETs while static analyses often lead to over-pessimistic upper bounds [30].…”

Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators

“…More recently, [HFC14] gave formal semantics to an ADL tailored for timing analysis. This is done by means of constraint programming, allowing the use of constraint solvers to compute the WCET of basic blocks on complex architectures with out-of-order execution [HCFR13]. Given that the formal timed semantics is basically that of the WCET analysis model and is not operational, it is not clear how easy it is to relate it with the semantics of simulation models of the same architecture.…”

“…• Microarchitectural models used for pipeline simulation during WCET (Worst-Case Execution Time) analysis [HCFR13], [HFC14], [HRP17]. These models are used to compute safe over-approximations of the duration of a sequential piece of code, i.e., one function running without interruption on a processor core).…”

Formal Architecture Specification for Time Analysis

“…The pipeline analysis consists of modeling the instruction behavior of the pipeline and evaluating the impact of the hardware features on the instruction execution times [17]. The framework OTAWA was enhanced with an ADL-based approach [11] that aims at computing the time cost of a basic block considering the pipeline features. The carried analysis considers as input (1) the program binary, (2) the basic block as an instruction sequence and (3) the architecture description in the Sim-nML language [10] (see figure 1).…”

“…The attribute image gives the binary representation and action defines the semantics of the instruction (register transfer). Our extension to the Sim-nML language [11] allows the definition of the processor resources and the execution model of the instruction set, giving how and when the resources are accessed by each instruction. The properties of the hardware components are specified as attributes.…”