Hardware assistance for trustworthy systems through 3-D integration

Abstract

Hardware resources are abundant; state-of-the-art processors have over one billion transistors. Yet for a variety of reasons, specialized hardware functions for high assurance processing are seldom (i.e., a couple of features per vendor over twenty years) integrated into these commodity processors, despite a small flurry of late (e.g., ARM TrustZone, Intel VT-x/VT-d and AMD-V/AMD-Vi, Intel TXT and AMD SVM, and Intel AES-NI). Furthermore, as chips increase in complexity, trustworthy processing of sensitive information can become increasingly difficult to achieve due to extensive on-chip resource sharing and the lack of corresponding protection mechanisms. In this paper, we introduce a method to enhance the security of commodity integrated circuits, using minor modifications, in conjunction with a separate integrated circuit that can provide monitoring, access control, and other useful security functions. We introduce a new architecture using a separate control plane, stacked using 3-D integration, that allows for the function and economics of specialized security mechanisms, not available from a coprocessor alone, to be integrated with the underlying commodity computing hardware. We first describe a general methodology to modify the host computation plane by attaching an optional control plane using 3-D integration. In a developed example we show how this approach can increase Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ACSAC '10 Dec. 6-10, 2010, Austin, Texas USA Copyright 2010 ACM 978-1-4503-0133-6/10/12 ...$10.00. system trustworthiness, through mitigating the cache-based side channel problem by routing signals from the computation plane through a cache monitor in the 3-D control plane. We show that the overhead of our example application, in terms of area, delay and performance impact, is negligible.

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…To address and manage this challenge of verification and other security-centric challenges, the notions of "secure by design" and "design-for-trust" have been promoted for some years now for "regular" 2D chips [116], [117], [118], [119], [123], [124], [125], [126], [127], [128]. Similar studies are recently focusing on 3D chips as well [129], [130], [131], [132], [133], [134], [135], [136], [137], [138]. Note that early stud- Fig.…”

“…9 Abstract scheme of Refs. [129], [130]. Each security feature requires an introspective interface (TSVs, in red) between the controller/security die and the untrusted commodity die, along with some additional transistors for the latter (not illustrated).…”

“…With that challenge in mind, one particularly aspiring solution towards trustworthy chips are hardware monitors or wrappers for the continuous and pervasive control of untrusted and/or security-critical components [129], [130], [139], [148], [149], [150], [151]. The moment such monitors/wrappers observe some malicious behaviour, i.e., any behavioural anomaly with respect to well-defined, "normal" patterns (which may also be re-programmed if need arises), the related components are overridden or isolated.…”

“…The notion of monitors is especially attractive in the context of 3D integration; untrustworthy components in one die may be controlled in a precise and localized manner with the help of monitoring components implemented in another die [129], [130], [139]. For example, Valamehr et al [129], [130] propose powerful security features acting on the gate-and transistor-level, based on introspective TSV interfaces (Fig.…”

“…For example, Valamehr et al [129], [130] propose powerful security features acting on the gate-and transistor-level, based on introspective TSV interfaces (Fig. 9).…”