Hardware-assisted power estimation for design-stage processors using FPGA emulation

Hesselbarth, Sebastian; Baumgart, Tim; Blume, Holger

doi:10.1109/patmos.2014.6951877

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…Several other works have also been inspired from the profile-driven approaches presented by Senn et al 18 and Rethinagiri et al, 20 but they focused on the application layer, such as enhancing the efficiency of smartphones or applications running on an embedded platform. [23][24][25]…”

Section: Profile-driven Power/energy Estimationmentioning

confidence: 99%

A simulation framework for code-level energy estimation of embedded soft-core processors

et al. 2017

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This contribution presents a simulation framework for code-level energy estimation of open-source MIPS-R2000, LEON3, and openMSP430 embedded soft-core processors. The method proposed in this work is generic and can be extended to other processors and architectures. The framework consists of two modules as follows. (i) An instruction-level power estimator module that estimates the average power consumption of individual machine instructions simulated using gate-level net-lists of the target processors. This module is used to create instruction-level power consumption databases of the target processor. (ii) A high-level energy estimation module parses the assembly code written for a target processor and gives the estimated energy consumed while taking the inherent data and control dependencies into consideration. Our proposed framework, therefore, provides rapid offline code-level energy estimation using simulations and avoids the low-level hardware estimation overheads. The energy estimation time efficiency of our proposed methodology is evaluated by using different benchmarks against the results of other existing energy estimation frameworks, such as SoftExplorer, TLM with the ISS-based simulation tool, SimplePower/WATTCH, and EPEM. These results indicate that our proposed framework is roughly one to two orders of magnitude faster in energy estimation. From the accuracy perspective, our energy estimations lie, on average, within 2% of those obtained from WATTCH. The proposed tool is especially useful in estimating the algorithmic energy efficiency of various codes targeted at low/moderate-end embedded systems, such as wireless sensor network nodes.

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Section: Profile-driven Power/energy Estimationmentioning

confidence: 99%

A simulation framework for code-level energy estimation of embedded soft-core processors

et al. 2017

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“…FPGA emulation is another approach that is more and more used to accelerate power estimation. In fact, power models are implemented into a FPGA in order to estimate the power consumption at the speed of the device [38]. Power estimations can be performed in few milliseconds once the power models have been developed.…”

Section: Related Workmentioning

confidence: 99%

“…In fact, such techniques have been widely studied and aim at extrapolating power as a function of parameters of interest [32]- [36], [38]. In our case, analytical power models have been developed using curve fitting and linear regressions.…”

Section: ) Analytical Power Modelsmentioning

confidence: 99%

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

2016

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FPGA emulation methodology for fast and accurate power estimation of embedded processors

Hesselbarth

Schewior

Blume

2017

Journal of Systems Architecture

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Hardware-assisted power estimation for design-stage processors using FPGA emulation

Cited by 5 publications

References 17 publications

A simulation framework for code-level energy estimation of embedded soft-core processors

A simulation framework for code-level energy estimation of embedded soft-core processors

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

FPGA emulation methodology for fast and accurate power estimation of embedded processors

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