Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

Abstract

Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardwarebased mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

Masked SABL: A Long Lasting Side-Channel Protection Design Methodology

“…In this case, we actually observe HCI effects, which -as stated in Section II-B -is one of the dominant factors among the aging mechanisms. Although several techniques have been proposed to mitigate the aging effects from a reliability perspective [6], [12], a few studies concern the impact of aging on the circuits security [13]. Since aging is inevitable, we look for a technique to somehow force the corresponding transistors to age identically, rather than avoiding the HCI.…”

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“…However, it does not provide a method to run the scheme, analyzes simplistic workloads and only targets the Negative BTI (NBTI) aging mechanism. The authors of [18] propose a hardware-based mitigation scheme for address decoders that takes advantage of idle cycles to change the decoder's address input, thereby reducing static BTI stress. A downside of that approach comes from its hardware overhead (area, power and delay).…”