Hardware-Based Linear Program Decoding With the Alternating Direction Method of Multipliers

Abstract

We present a hardware-based implementation of Linear Program (LP) decoding for binary linear codes. LP decoding frames error-correction as an optimization problem. In contrast, variants of Belief Propagation (BP) decoding frame error-correction as a problem of graphical inference. LP decoding has several advantages over BP-based methods, including convergence guarantees and better error-rate performance in high-reliability channels. The latter makes LP decoding attractive for optical transport and storage applications. However, LP decoding, when implemented with general solvers, does not scale to large blocklengths and is not suitable for a parallelized implementation in hardware. It has been recently shown that the Alternating Direction Method of Multipliers (ADMM) can be applied to decompose the LP decoding problem. The result is a message-passing algorithm with a structure very similar to BP. We present new intuition for this decoding algorithm as well as for its major computational primitive: projection onto the parity polytope. Furthermore, we present results for a fixed-point Verilog implementation of ADMM-LP decoding. This implementation targets a Field-Programmable Gate Array (FPGA) platform to evaluate error-rate performance and estimate resource usage. We show that Frame Error Rate (FER) performance well within 0.5dB of double-precision implementations is possible with 10-bit messages. Finally, we outline a number of research opportunities that should be explored en-route to the realization of an Application Specific Integrated Circuit (ASIC) implementation capable of gigabit per second throughput.

Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview

“…The most challenging part of ADMM-based LP decoding from a hardware implementation perspective is the so-called step of Euclidean projection onto the parity polytope. Indeed, there are many recent works that aim to reduce the complexity and to describe efficient hardware architectures for this step (e.g., [24,20,25,26] and references therein). Even though significant advances have been made in the past few years, there is still significant room for improvement, especially in the direction of LP decoding hardware architectures that are competitive with other state-of-the-art decoders in terms of throughput, resource utilization, and energy efficiency (cf.…”

“…Due to space constraints we skip the details of this relaxation, which can be found in, e.g.,[19, Sec. III] or[20, Sec. II].…”

ADMM-Based ML Decoding: from Theory to Practice

“…There are various problems that can cause a loss of the ML certificate: First, as pointed out in [12], using a penalized version of the ADMM removes the ML certificate property, although a penalization term can largely improve the errorcorrecting performance of pure LP decoding. Second, terminating the ADMM after a maximum number of iterations removes the ML certificate property, as the algorithm might be stopped before it has converged to its final solution.…”

“…In addition to improvements on algorithmic level, further speedup can be achieved by using dedicated hardware accelerators. A first step towards hardware-based ML decoding has been made in [12], where the ADMM as LP decoder has been implemented on an FPGA. However, this was not considered in the context of ML decoding.…”

Decoding Nonbinary LDPC Codes via Proximal-ADMM Approach (include convergence proofs)

“…In comparison with the proposed proximal-ADMM decoders, non-penalized/penalized decoders in[38] need less variables/checks. Usually, this merit leads the decoder to costing less dynamic power[47] when implementing it using an FPGA chip. Their decoding procedure involves high-dimensional Euclidean projections, which have to be implemented in series.…”