2022 International Electron Devices Meeting (IEDM) 2022
DOI: 10.1109/iedm45625.2022.10019393
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Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

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“…IBM has also demonstrated vertical channel NS transistors fabricated using a T-D approach, as shown in Fig. 8(d) [ 78 , 87 ]. These devices show high electrical performance and indicate that VGAAFETs may enable scaling beyond the limits of lateral GAAFETs.…”
Section: New Paths To a Vertical Transistormentioning
confidence: 99%
“…IBM has also demonstrated vertical channel NS transistors fabricated using a T-D approach, as shown in Fig. 8(d) [ 78 , 87 ]. These devices show high electrical performance and indicate that VGAAFETs may enable scaling beyond the limits of lateral GAAFETs.…”
Section: New Paths To a Vertical Transistormentioning
confidence: 99%
“…The dynamic random-access memory (DRAM) roadmap of the International Roadmap for Devices and Systems (IRDS) 2020 report proposes that the cell transistor structure of DRAM will shift from one of the current mainstream Saddle Fin to the vertical channel transistor (VCT) [ 6 , 7 , 8 , 9 , 10 , 11 ]. In logic applications, IBM and Samsung jointly proposed vertical-transport FET (VTFET), which achieved a 40 nm contacted gate pitch (CGP) under excellent gate control, which is significantly lower than the 45 nm CGP of the TSMC 3 nm fin field-effect transistor (FinFET) technology node [ 12 , 13 , 14 ]. This proves that the vertical device has great potential for future device footprint scaling.…”
Section: Introductionmentioning
confidence: 99%
“…However, there is a problem with metal elements, such as Au contamination, so it is not compatible with the standard CMOS process. In addition, the "top-down" approach to fabricating vertical transistor devices through lithography and etching processes has been reported by Samsung and IBM [16,17]. However, there are some problems with this route.…”
Section: Introductionmentioning
confidence: 99%