Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing

Convent, Lukas; Hungerecker, Sebastian; Scheffel, Torben; Schmitz, Malte; Thoma, Daniel; Weiß, Alexander

doi:10.1007/978-3-030-03769-7_5

Cited by 10 publications

(5 citation statements)

References 19 publications

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“…Alternatively, the FPGA can function as an instrument for observing the CPU and its software in real-time. For example, we perform runtime verification of a combined hardware/software system at scale with zero overhead, by using the FPGA to process events from the program trace units on the ThunderX-1 cores, and compiling temporal logic assertions about the behavior of the hardware, OS, and application software into reconfigurable logic [17].…”

Section: Further Use-casesmentioning

confidence: 99%

Enzian: an open, general, CPU/FPGA platform for systems software research

Cock

Ramdas

Schwyn

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Section: Further Use-casesmentioning

confidence: 99%

Enzian: an open, general, CPU/FPGA platform for systems software research

Cock

Ramdas

Schwyn

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…The flexibility of the TeSSLa language allows expressing different kinds of analyses for functional or timing properties in terms of stream events. A TeSSLa specification is then compiled to a configuration of the Event Processing Units (EPUs) [7] of the monitoring unit, which are specialised units on the FPGA implementing low-level TeSSLa stream operations. The events of the TeSSLa streams are efficiently processed by the EPUs in the trace box.…”

Section: Coems Infrastructurementioning

confidence: 99%

Hardware-Assisted Online Data Race Detection

Ahishakiye

Jarabo²,

Pun

et al. 2021

Formal Methods in Outer Space

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Dynamic data race detection techniques usually involve invasive instrumentation that makes it impossible to deploy an executable with such checking in the field, hence making errors difficult to debug and reproduce. This paper shows how to detect data races using the COEMS technology through continuous online monitoring with low-impact instrumentation on a novel FPGA-based external platform for embedded multicore systems. It is used in combination with formal specifications in the high-level stream-based temporal specification language TeSSLa, in which we encode a lockset-based algorithm to indicate potential race conditions. We show how to instantiate a TeSSLa template that is based on the Eraser algorithm, and present a corresponding light-weight instrumentation mechanism that emits necessary observations to the FPGA with low overhead. We illustrate the feasibility of our approach with experimental results on detection of data races on a sample application.

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“…Two other extensions of L are TeSSLa and Striver. TeSSLa [10] allows for monitoring piece-wise constant signals where streams can emit events at different speeds with arbitrary latencies. It relies on the instrumentation of C code and is thus not independent of the monitored system.…”

Section: Related Workmentioning

confidence: 99%

“…Moreover, the monitor is highly space and energy efficient. Unlike interpreter-based approaches [10,12], which include a general-purpose runtime environment, the compiled circuit is strictly limited to the operations that actually occur in the specification. As a result, the monitors of our case studies are able to run on small FPGA boards with li le power (< 2 W).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FPGA Stream-Monitoring of Real-time Properties

Baumeister

Finkbeiner

Schwenger

et al. 2019

ACM Trans. Embed. Comput. Syst.

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An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at runtime greatly increases the confidence in a safe execution. Such a monitor needs to be based on a specification language capable of expressing complex, highlevel properties using only the accessible low-level signals. Moreover, tight constraints on computational resources exacerbate the requirements on the monitor. us, several existing approaches to monitoring are not applicable due to their dependence on an operating system.We present an FPGA-based monitoring approach by compiling an RTL specification into synthesizable VHDL code. RTL is a stream-based specification language capable of expressing complex real-time properties while providing an upper bound on the execution time and memory requirements. e statically determined memory bound allows for a compilation to an FPGA with a fixed size. An advantage of FPGAs is a simple integration process in existing systems and superb executing time. e compilation results in a highly parallel implementation thanks to the modular nature of RTL specifications. is further increases the maximal event rate the monitor can handle.

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Hardware-Based Runtime Verification with Embedded Tracing Units and Stream Processing

Cited by 10 publications

References 19 publications

Enzian: an open, general, CPU/FPGA platform for systems software research

Enzian: an open, general, CPU/FPGA platform for systems software research

Hardware-Assisted Online Data Race Detection

FPGA Stream-Monitoring of Real-time Properties

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