Hardware design and implementation of 3780 points FFT based on FPGA in DTTB

Yang, Xiaogang; Wei, Du; Yang, Zhanxin; Li, Rui; Wang, Xiaoguang

doi:10.1109/icaict.2010.5611806

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…SDF FFT architectures are the most common pipelined architectures used to process NP2 FFTs [19], [21], [22], [23], [24], [25], [26], [27]. Fig.…”

Section: Sdf Fft Architecturesmentioning

confidence: 99%

“…Nowadays, pipelined FFT hardware architectures for NP2 sizes mostly consider single-path delay feedback (SDF) architectures [18], [19], [20], [21], [22], [23], [24], [25], [26], with the exception of [27]. However, for NP2 sizes, SDF architectures are not as efficient as could be expected: Although SDF architectures process data in series at a rate of one sample per clock cycle, the butterflies that they use operate data in parallel.…”

mentioning

confidence: 99%

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Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

Bautista

Garrido

López‐Vallejo

2023

IEEE Trans. Circuits Syst. I

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This paper presents new serial butterflies for nonpower-of-two (NP2) fast Fourier transform (FFT) architectures. The paper considers radices 2, 3, 4, and 5, which are used in FFTs for 5G systems. Current designs for non-power-of-two FFTs are mostly based on the single-path delay feedback (SDF) architecture. This type of architecture processes data arriving in series. However, it uses butterflies with several parallel inputs. This results in low utilization, as the butterflies have to wait for all the inputs before they start to process them. Conversely, the proposed approach allows to calculate the butterflies on data that arrive in series. This removes waiting times and reduces the number of hardware components such as multipliers and adders. As a result, the proposed butterflies achieve high performance and provide a significant reduction in area and power consumption with respect to parallel butterflies. Thus, they are an efficient solution when data must be processed in series in the butterflies.

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“…SDF FFT architectures are the most common pipelined architectures used to process NP2 FFTs [19], [21], [22], [23], [24], [25], [26], [27]. Fig.…”

Section: Sdf Fft Architecturesmentioning

confidence: 99%

mentioning

confidence: 99%

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

Bautista

Garrido

López‐Vallejo

2023

IEEE Trans. Circuits Syst. I

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“…In multicarrier mode DTMB runs in 4K mode with 3780 sub-carriers which are spaced apart at 2 kHz in the 8 Most communication modules, including FFT, are normally implemented using hardwired ASICs or FPGA [2][3][4][5], but they are meeting great challenges due to the rapidly proliferating of protocols. Different protocols require different codes, and hardware designed for one protocol cannot work for another one.…”

Section: Introductionmentioning

confidence: 99%

Efficient implementation of 3780-point FFT on a 16-core processor

Yang

Chen

Xie

et al. 2013

2013 IEEE 10th International Conference on ASIC

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The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.

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