2021 IEEE 15th International Conference on Anti-Counterfeiting, Security, and Identification (ASID) 2021
DOI: 10.1109/asid52932.2021.9651693
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Hardware Design of SHA-3 for PQC Classic McEliece

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“…On the one hand, the input stage is formed by the number of XOR operations according to the bitrate, which is in this case 576 bits for SHA3-512. This strategy, mentioned in [12], allows to reduce the number of resources used since the input block size must be concatenated with zeros to reach the 1600 bits of the Keccak input. On the other hand, the Keccak core design strategy has followed the architecture first presented in [15] that is also used in other works such as [7], [8] or [16].…”
Section: A Basic Versionmentioning
confidence: 99%
See 1 more Smart Citation
“…On the one hand, the input stage is formed by the number of XOR operations according to the bitrate, which is in this case 576 bits for SHA3-512. This strategy, mentioned in [12], allows to reduce the number of resources used since the input block size must be concatenated with zeros to reach the 1600 bits of the Keccak input. On the other hand, the Keccak core design strategy has followed the architecture first presented in [15] that is also used in other works such as [7], [8] or [16].…”
Section: A Basic Versionmentioning
confidence: 99%
“…Another approaches look for a competitive result in terms of efficiency with a good balance between throughput and area in [10] and [11]. More recently, a hardware design and implementation of the SHA-3 algorithm on FPGA is presented in [12].…”
Section: Introductionmentioning
confidence: 99%