Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems

Kalantari, Fereshteh; Hosseini-Nejad, Hossein; Sodagar, Amir M.

doi:10.1109/tvlsi.2022.3170596

Cited by 11 publications

(9 citation statements)

References 32 publications

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“…Fig. 15 compares the clustering accuracy achieved by our NSP against well-established and commonly used offline software algorithms [8] and state-ofthe-art online spike-sorting chips [14], [15], [16], [17] for the two different ground-truth datasets. Our fixed-point simulations show that for the multichannel Neuropixels datasets, the clustering accuracy of our NSP outperforms two software tools and is close to the highest level on every dataset.…”

Section: A Simulation Resultsmentioning

confidence: 99%

“…Compared with recently reported on-chip spike sorters, this work achieves the highest number of input channels and the smallest area per channel thanks to our careful co-optimizations between the algorithms and the circuitarchitecture decisions. Despite the extra complexity added by the spatiotemporal dimensionality and the higher input bitwidth (12 bits) and sampling rate (30 kHz), we achieve a power consumption comparable to [16], [17] by reducing the computational complexity based on the geometry information of the electrode array. While the design in [14] achieves a high number of channels with much lower power, that work uses a lower input bit-width and sampling rate, a smaller SRAM (39 kB), and highly empirical SD and FE algorithms that do not require multipliers, but that may not be applicable to different spike shapes.…”

Section: B Measurement Resultsmentioning

confidence: 99%

“…To this end, a lot of efforts have been devoted to efficient embedded NSP. Although a few initial works only implemented SD and FE on a chip [9], [10], [11], several multichannel, online spike-sorting chips have been reported in recent years for full-chain signal processing [12], [13], [14], [15], [16], [17], [18]. In [13], a neural spike processor integrated with a power management unit achieves extremely high power efficiency, but it requires offline clustering pretraining to extract the cluster parameters before the online phase, making it less ideal for real online applications.…”

Section: Introductionmentioning

confidence: 99%

“…The low power and area efficiencies of this implementation, however, impede its suitability for high-channel-count systems. The unsupervised online spike sorter reported in [16] performs on-the-fly NSP. Unfortunately, its processing latency scales linearly with the number of clusters, preventing its application in high-channel-count interfaces.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

Chen,

Tacca,

Chen

et al. 2023

IEEE J. Solid-State Circuits

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As neural-recording devices get denser and generate more data due to ever higher channel counts, on-chip and online neural signal processor (NSP) becomes crucial to reduce the data-transmission power and to enable real-time closed-loop applications with minimum latency. For this purpose, we report an online spike-sorting integrated circuit (IC) able to process neural signals from 384 channels with software-comparable accuracy. By combining three main innovations, our design drastically improves the fundamental trade-off between hardware resources and real-time performance. Specifically, a central spike detection (CSD) algorithm is designed to mitigate the impact of redundant spikes on accuracy. Second, a peak first and second derivative extrema (FSDE) method is devised to accomplish robust feature extraction (FE) across various datasets. Finally, to deal with the trade-off between accuracy and complexity in the clustering stage, a geometry-aware OSort (Geo-OSort) algorithm is developed. A prototype chip has been fabricated in a 22 nm FDSOI CMOS process. The measurement results show that the designed NSP achieves an area of 0.0013 mm 2 /channel, a power consumption of 1.78 µW/channel, a latency of 33.9 µs, and an accuracy of 97.7% without clustering pretraining.

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Section: A Simulation Resultsmentioning

confidence: 99%

Section: B Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

Chen,

Tacca,

Chen

et al. 2023

IEEE J. Solid-State Circuits

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show abstract

“…The step of feature extraction within the spike-sorting system is used in order to select, among all the samples collected to represent the spike waveform, the more discriminative ones, which are used to obtain a sort of dimensionality reduction of the data, to be used in the following clustering phase. The main features extraction approaches adopted in the literature are [18] as follows:…”

Section: Features Extraction Approachesmentioning

confidence: 99%

Real-Time Compact Digital Processing Chain for the Detection and Sorting of Neural Spikes from Implanted Microelectrode Arrays

Vittimberga,

Corelli,

Scotti

2024

Chips

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Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm2/ch, 7.16 μW/ch, 0.0168 mm2/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively.

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Neuronal Multi Unit Activity Processing with Metal Oxide Memristive Devices

Sbandati,

Jiang,

Yadav

et al. 2024

Adv Elect Materials

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Intra‐cortical brain‐machine interfaces (BMIs), able to decode neural activity in real‐time, represent a revolutionary opportunity for treating medical conditions. However, traditional systems focusing on single‐neuron spike detection require high processing rates and power, hindering the up‐scaling for neurons‐population monitoring in clinical application. An intriguing proposition is the memristive integrating sensor (MIS) approach, which uses resistive RAM (RRAM) for threshold‐based neural activity detection. MIS leverages analogue multi‐state switching properties of metal‐oxide RRAM to compress neural inputs by encoding above‐threshold events in resistance displacement, facilitating efficient data down‐sampling in the post‐processing, enabling low‐power, high‐channel systems. Initially tested on spikes and local field potentials, here MIS is adapted to process multi‐unit activity envelope (eMUA)—the envelope of entire spiking activity—which has recently been proposed as crucial input for real‐time neuro‐prosthetic control. Prior necessary modifications to the MIS for effective operation, this adaptation achieved over 95% sensitivity across two types of metal‐oxide devices: Pt/TiOx/Pt and TiN/HfOx/TiN, proving its platform‐agnostic capabilities. Furthermore, towards the integration of MIS with silicon chips, it is shown that it can reduce total system power consumption to below 1 µW, as RRAM encoding stage relaxes the signal preservation and noise requirements that challenge traditional complementary metal‐oxide‐semiconductor (CMOS) front‐ends. This eMUA‐MIS adaptation offers a viable pathway for developing more scalable and efficient BMIs for clinical use.

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Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems

Cited by 11 publications

References 32 publications

An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

Real-Time Compact Digital Processing Chain for the Detection and Sorting of Neural Spikes from Implanted Microelectrode Arrays

Neuronal Multi Unit Activity Processing with Metal Oxide Memristive Devices

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