2022
DOI: 10.1109/tce.2022.3163345
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Hardware-Friendly Multiple Transform Selection Module for the VVC Standard

Abstract: The H.266/versatile video coding (VVC) standard is the most recent ITU/ISO video coding standard finalized in July 2020. VVC includes several new coding tools at different levels of the coding scheme. These coding tools enable a significant bitrate saving of up to 50% for the same subjective video quality than its predecessor H.265/high efficiency video coding (HEVC). Among these tools, we can cite the multiple transform selection (MTS) which selects at the encoder horizontal and vertical transforms among thre… Show more

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Cited by 8 publications
(8 citation statements)
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“…In [ 39 ], an entropy-based method was proposed to replace the standard rate estimation. In [ 40 ], the approximation of DCT-VII was modelled to reduce the computation. By combining the histogram of oriented gradient features and the depth information, Wang et al.…”
Section: Related Workmentioning
confidence: 99%
“…In [ 39 ], an entropy-based method was proposed to replace the standard rate estimation. In [ 40 ], the approximation of DCT-VII was modelled to reduce the computation. By combining the histogram of oriented gradient features and the depth information, Wang et al.…”
Section: Related Workmentioning
confidence: 99%
“…Compared with HEVC, the QTMT division used in VVC can generate more types of subunits and can better adapt to different video contents. In VVC, there are six ways to classify CU, as shown in Figure 1: Non-split (NS), quadrinomial tree (QT), vertical binary tree (BTV), horizontal binary tree (BTH), vertical trinomial tree (TTV), and horizontal trinomial tree (TTH) [2] . These six division patterns can form a candidate list, and the optimal pattern 𝑛 * is the pattern with the smallest RD Cost in the candidate list 𝑛.…”
Section: Introductionmentioning
confidence: 99%
“…1 𝑅𝐷 𝐶𝑜𝑠𝑡 = 𝑆𝑆𝐸 + 𝜆 × 𝐵𝑖𝑡 𝑚𝑜𝑑𝑒 (1) 𝑛 * = 𝑛 𝑚𝑖𝑛 𝑅𝐷 𝐶𝑜𝑠𝑡 (2) Where SSE is the distortion of luminance and chrominance, 𝐵𝑖𝑡 𝑚𝑜𝑑𝑒 is the cost of in-frame prediction, and λ is the Lagrangian multiplier. 𝑛 1 contains six division modes, NS, QT, VBT, HBT, VTT, and HTT, and 𝑛 2 contains five division modes, NS, VBT, HBT, VTT, and HTT.…”
Section: Introductionmentioning
confidence: 99%
“…2) Hardware implementations of VVC codec on FPGA and ASIC devices. The papers accepted for publication in this special issue are briefly described, for more details, the reader may refer to the corresponding paper [5]- [9]. These papers address different aspects to design real time VVC encoders and decoders from tools optimizations [5], [6] for software and hardware VVC decoders, complexity reduction of VVC encoder [7], [9] to the design of real time software VVC encoders [8].…”
mentioning
confidence: 99%
“…Additionally in terms of resources needed for the implementations, the use of the three transforms MTS increases the memory usage because it is needed to store more coefficients. Authors in [5] proposed an efficient approximation of the DST-VII based on the DCT-II and adjustment stage. This approximation has been solved as an integer optimization problem.…”
mentioning
confidence: 99%