Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC

Kthiri, Moez; Loukil, Hassen; Imen, Werda; Atitallah, Ahmed Ben; Samet, Amine; Nouri, Mohammad

doi:10.1109/ssd.2009.4956714

Cited by 10 publications

(7 citation statements)

References 5 publications

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“…The Table 4 presents a comparison among this work and the works [6] and [7]. Our solution reached the highest operation frequency among other works, using a similar amount of hardware resources.…”

Section: Related Workmentioning

confidence: 85%

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High efficient motion estimation architecture with integrated Motion Compensation and FME support

Sanchez

Noble

Porto

et al. 2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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This paper presents an efficient architecture for Motion Estimation (ME) based on the Diamond Search (DS) Algorithm. This architecture also includes the Motion Compensation (MC) for luminance samples, reusing internal ME results and avoiding the additional external memory accesses for the MC operation. The proposed architecture also generates inputs for a Fractional Motion Estimation (FME) for quarter sample precision, as proposed by the H.264/AVC standard. The main goal of this work is to design a low cost ME architecture for the DS algorithm with reduced number of external memory accesses and ready to be integrated with a fractional interpolator. The designed architecture was synthesized to Altera Stratix 4 family of FPGAs and in the worst case scenario, this architecture is able to process Full HD (1080p) videos in real time.

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Section: Related Workmentioning

confidence: 85%

“…The work [7] performs the Large Diamond Parallel Search (LDPS), which is another sub-optimal algorithm. The block size used is 16x16.…”

Section: Related Workmentioning

confidence: 99%

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High efficient motion estimation architecture with integrated Motion Compensation and FME support

Sanchez

Noble

Porto

et al. 2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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“…Hardware-oriented modified DS (HMDS) [7] is using three fixed iterations with two shapes and provides better encoding quality for centre biased low motion sequences. Another variant line diamond parallel search (LDPS) [8] is using small diamond pattern and demonstrates speedup with poor quality. Dynamic multipoint DS [9] algorithm begins the search from four locations in addition to the centre; hence need more parallel PEs to compute the best match.…”

Section: Hardware Implementationsmentioning

confidence: 99%

Register array‐based sum of absolute difference processor with parallel memory system for fast motion estimation

Shah¹,

Dalal²

2018

IET Computers & Digital Techniques

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Fast search block matching algorithm (BMA)-based video coding provides reasonable good quality video with minute cost of computation. In fast BMA, clock cycles required to read pixel data are quite more compared with matching operation due to erratic location of candidate macroblocks (CMBs). With aim of reduction in number of clock cycles, parallel memory system is used in this study, which can accelerate reading of CMBs and speedup motion vector (MV) computation. Novel concept of register array is introduced to organise CMBs, which expedite computation hungry search process. Owing to shape of register array, lesser space is needed to store CMBs and architecture addresses wide range of search patterns. The proposed sum of absolute difference processor with parallel memory system computes MV of 1 macroblock in 28 clock cycles in average case. Compared to single memory system, it saves 68% and 80% clock cycles in CMB access of initial search and intermediate search process, respectively. Hardware architecture is tested with Xilinx Virtex5 field programmable gate array. The proposed fixed 8×8 macroblock size architecture processes 354 high definition (HD) (1080p) frames per second (fps) and configurable architecture processes 201 HD fps which is more than adequate for real-time encoding.

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“…To achieve this, various graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and very-large-scale integration (VLSI) architectures are employed for motion estimation in [6,7]. Moreover, a fast block matching algorithm (BMA) is implemented in the hardware, considering the maximum utilisation of the resources in the H.264 framework [8,9].…”

Section: Introductionmentioning

confidence: 99%