Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Rais, Muhammad H.

doi:10.3844/ajeassp.2010.201.206

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…Field Programmable Gate Arrays (FPGAs) are good choice for hardware realization but with limitations in design optimization. Furthermore, FPGA implementation is good for prototyping where, the aim is to predict the behavior of design in real world applications, there are many DSP systems reported in literature few of them are (Palaniappan and Zulkifli, 2007;Benhamid and Othman, 2009;Rais et al, 2010;Rais, 2010;Teymourzadeh et al, 2010). Application Specific Integrated Circuits (ASIC) is the most feasible technology to realize DSP algorithms and any other complex algorithm, without much limitations in optimizing the design.…”

Section: Introductionmentioning

confidence: 99%

Application Specific Integrated Circuits Design and Implementation of Rademacher and Walsh Functions

Abbasi¹,

Alamoud²,

Abbasi³

2013

American Journal of Engineering and Applied Sciences

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The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today's DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. Optimized VHDL models have been developed and used for design entry. The design is thoroughly verified using advanced verifications tools. The design is implemented and processing has been done with 90 nm CMOS Technology from TSMC foundry. It is observed that the results obtained, are far better than the FPGA implementation reported earlier in the literature.

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Section: Introductionmentioning

confidence: 99%

Application Specific Integrated Circuits Design and Implementation of Rademacher and Walsh Functions

Abbasi¹,

Alamoud²,

Abbasi³

2013

American Journal of Engineering and Applied Sciences

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“…A number of research efforts have been reported for making low power multipliers Rais, 2009a;2009b;Rais, 2010a;2010b;Rais et al, 2010;Rais and Al Mijalli, 2011a;2011c).…”

Section: Introductionmentioning

confidence: 99%

Field Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's Multipliers

Rais¹

2011

Journal of Computer Science

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Abstract:Problem statement: Parallel array multipliers are required to achieve high execution speed for Digital Signal Processing (DSP) applications. Approach: The purpose of this article is to investigate Field Programmable Gate Arrays (FPGAs) implementation of standard Braun's multipliers on Spartan-3AN, Virtex-2, Virtex-4 and Virtex-5 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using Analysis Of Variance (ANOVA) method using the software Statistical Package for Social Science (SPSS) with a 0.05 confidence level was used to compare the FPGA devices. Results: The FPGA resource utilization by Virtex-5 is the lowest in value for 4×4, 6×6, 8×8 and 12×12-bit Braun's multipliers as compared to Spartan-3AN, Virtex-2 and Virtex-4 FPGAs. The average connection delays in Virtex-2 shows consistency and gradual increase in value as the size of multiplier increased. Virtex-2 FPGA demonstrates lower average connection delays as compared to Spartan-3AN, Virtex-4 and Virtex-5 FPGAs. For the maximum pin delay same observations are obtained for Virtex-2 FPGA. The anomalies in maximum pin delay and average connection delay are observed in Virtex-5, Virtex-4 and Spartan-3AN FPGAs. FPGA devices also demonstrate that as the size of multipliers increases their mean latency value is also increases. Conclusion: The FPGA resource utilization by Virtex-5 is the lowest in value for 4×4, 6×6, 8×8 and 12×12-bit Braun's multipliers as compared to Spartan-3AN, Virtex-2 and Virtex-4 FPGAs. Even value obtained for Virtex-5 FPGA for 4×4 bit standard Braun's multiplier for number of occupied slices and look up tables are lower in value than reported in literature.

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“…This is more pronounced in digital signal processing (DSP) applications that constitute large number of multiplications. In the DSP computational complexity of algorithms has increased to such extent that they require fast and efficient parallel multipliers (Agostini et al, 2007;Gierenz et al, 2010;Kong et al, 2008;Zemva and Verderber, 2007;Rais, 2009a;2009b;Rais, 2010;Rais et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

“…For this purpose, the Field Programmable Gate Arrays (FPGAs) have emerged as a platform of choice for efficient hardware implementation and an attractive alternative to Application Specific Integrated Circuits (ASICs) (Rais, 2009a;2009b;Rais, 2010;Rais et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

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Field Programmable Gate Arrays Based Realization of Truncated Multipliers

Rais¹

2011

American Journal of Applied Sciences

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Problem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation results of truncated multipliers on Sparatn-3An FPGA showed significant improvement as compared to Virtex and Virtex-E FPGA devices. Conclusion: Truncated multipliers can be used in medical imaging technology such as CT scan.

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Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Cited by 11 publications

References 15 publications

Application Specific Integrated Circuits Design and Implementation of Rademacher and Walsh Functions

Application Specific Integrated Circuits Design and Implementation of Rademacher and Walsh Functions

Field Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's Multipliers

Field Programmable Gate Arrays Based Realization of Truncated Multipliers

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