Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Abstract

Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.Another more general method to solve this problem is to select the optimal switch admittance parameter, Gs. One possibility is to consider a priori the switch admittance parameter, and then find the corresponding optimum value by comparing the offline simulation results with the benchmark results to minimize the relative errors; however, such a trial-and-error method has a low efficiency [19]. Within this context, the paper proposes a novel approach to choose the optimal switch admittance parameter, Gs, by minimizing the switching loss to reduce the computations required and increase the simulation precision.The high parallelism offered by FPGAs and their potential to conduct a real-time simulation in the nanosecond range make these devices an emerging processor for real-time simulation of a complex power electronic system [20][21][22][23][24]. However, due to the limited FPGA hardware resources, it is especially important to balance FPGA resource consumption and simulation accuracy. Theoretically, precise simulation results could be obtained by excessive bit-length, but it would cause unnecessary FPGA resource consumption [25,26]. Meanwhile, with the purpose of decreasing the discretization process error, the simulation time step should be set as small as possible; however, the quantization error caused by a small simulation time step may reduce the simulation accuracy [27]. Some scholars conducted a related qualitative analysis respectively but lacked overall quantitative calculations. Therefore, how to precisely select the bit-length and simulation time step is a valuable task that needs to be solved in the realm of HIL real-time simulation in FPGA. Additionally, High-Level Synthesis tools such as, Vivado High Level Synthesis (VHLS) and OpenCL SDK [28,29], allow the use of high-level languages to ease the burden of design and verification of hardware, which reduces the development time and difficulty and improves ...

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

“…[28][29][30]. More recently, HLS has also been used for custom implementations of HS for HIL [26,31] and for its testbenches. The use of HLS for HIL has been shown to impose limitations on hardware performance and resource utilization when intended to be used in HS for HIL [11].…”

“…The circuit has been modelled using the ADC model. As previously discussed, the ADC is known to introduced fictitious oscillations and the conductance needs to be tuned [31]. The tuning was performed using the 2-norm relative error of the load currents [53]:…”

FPGA‐based hardware‐in‐the‐loop real‐time simulation implementation for high‐speed train electrical traction system

“…Traditional CPU-based HIL simulators, where the time step is usually in 40-100 μs range, can hardly take into accounts the entire switching event from pulse width modulation (PWM) in modern power electronics systems, so the multiple switching events within one fixed simulation time step h may produce erroneous simulation results [4][5][6][7]. The high parallelism provided by field-programmable gate array (FPGA) can compute the real-time simulation model from microsecond to nanosecond range, which is suitable for PEC with high-switching frequency [8][9][10].…”

Sliding Mode Output Regulation for a Boost Power Converter

“…Switched mode DC-DC power converters [1], are mainly used as constant current sources for LEDs, industry lighting, mobile phones, and photovoltaic systems [2,3]. Among the well known DC-DC converter topologies as buck, boost, buck-boost and cúk converters, the last three mentioned topologies result in being nonminimum-phase when directly controlling the output capacitor voltage variable [4].…”