Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.Another more general method to solve this problem is to select the optimal switch admittance parameter, Gs. One possibility is to consider a priori the switch admittance parameter, and then find the corresponding optimum value by comparing the offline simulation results with the benchmark results to minimize the relative errors; however, such a trial-and-error method has a low efficiency [19]. Within this context, the paper proposes a novel approach to choose the optimal switch admittance parameter, Gs, by minimizing the switching loss to reduce the computations required and increase the simulation precision.The high parallelism offered by FPGAs and their potential to conduct a real-time simulation in the nanosecond range make these devices an emerging processor for real-time simulation of a complex power electronic system [20][21][22][23][24]. However, due to the limited FPGA hardware resources, it is especially important to balance FPGA resource consumption and simulation accuracy. Theoretically, precise simulation results could be obtained by excessive bit-length, but it would cause unnecessary FPGA resource consumption [25,26]. Meanwhile, with the purpose of decreasing the discretization process error, the simulation time step should be set as small as possible; however, the quantization error caused by a small simulation time step may reduce the simulation accuracy [27]. Some scholars conducted a related qualitative analysis respectively but lacked overall quantitative calculations. Therefore, how to precisely select the bit-length and simulation time step is a valuable task that needs to be solved in the realm of HIL real-time simulation in FPGA. Additionally, High-Level Synthesis tools such as, Vivado High Level Synthesis (VHLS) and OpenCL SDK [28,29], allow the use of high-level languages to ease the burden of design and verification of hardware, which reduces the development time and difficulty and improves ...

The hardware-in-the-loop (HIL) real-time simulation for high-speed train electrical traction system aims to reduce the design cost and speed up control verification process of algorithms in the developmental stage of the traction control unit. In this study, based on the dSPACE real-time simulator, the multiple-simulator, multiple-simulation step of HIL real-time simulation system is first built. Second, for the associated discrete circuit modelling method, an optimisation method is proposed to minimise the switching loss and improve the simulation accuracy by selecting the optimal discrete-time switch admittance parameter, G S. To decrease the computational burden for field-programmable gate array (FPGA), a decoupling method without simulation latency is presented to reduce the matrix dimension of the system model. Finally, the real-time simulation models of electrical traction system are realised by CPU + FPGA-based simulator, in which the power electronics converter models are computed in FPGA with a fixed 100 ns time-step. The validity and reliability of the real-time simulation system is verified by the HIL simulation and experimental results, which indicate that the real-time HIL simulation at the nanosecond level improves the accuracy essentially.