Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Van, Lan-Da; Lu, Tse Min; Jung, Tzyy-Ping; Wang, Jo-Fu

doi:10.1109/icassp.2019.8682997

Cited by 11 publications

(30 citation statements)

References 19 publications

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“…However, the utilization of the MMA is not optimized, especially for complex-valued matrices. In addition, in [12] and [13], the preprocessor has to share computing units. The operating flow of these designs was not fully optimized, resulting in excessive processing delays.…”

Section: B Related Workmentioning

confidence: 99%

“…Table III compares the proposed centering and covariance units with prior work [10], [11], [13]. Since the implementation results reported in the literature are for the entire ICA system, the latency and complexity for the centering and covariance parts of the system were estimated for the prior designs.…”

Section: B Comparison With Prior Designsmentioning

confidence: 99%

“…However, the performance of this design is limited by the low operating frequency. Furthermore, [12] and [13] reported that they had improved the speed of ICA architectures by increasing the parallelism. However, the processing flow of the preprocessor is still sequential in nature and thus, cannot achieve high throughput.…”

Section: Introductionmentioning

confidence: 99%

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Configurable Independent Component Analysis Preprocessing Accelerator

Lu¹,

Shen²,

Fouda³

et al. 2022

Preprint

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Independent component analysis (ICA) has been used in many applications, including self-interference cancellation in in-band full-duplex wireless communication systems. This paper presents a high-throughput and highly efficient configurable preprocessor for the ICA algorithm. The proposed ICA preprocessor has three major components for centering, for computing the covariance matrix, and for eigenvalue decomposition (EVD). The circuit structures and operational flows for these components are designed both in individual and in joint sense. Specifically, the proposed preprocessor is based on a high-performance matrix multiplication array (MMA) that is presented in this paper. The proposed MMA architecture uses time-multiplexed processing so that the efficiency of hardware utilization is greatly enhanced. Furthermore, the novel processing flow of the proposed preprocessor is highly optimized, so that the centering, the calculation of the covariance matrix, and EVD are conducted in parallel and are pipelined. Thus, the processing throughput is maximized while the required number of hardware elements can be minimized. The proposed ICA preprocessor is designed and implemented with a circuit design flow, and performance estimates based on the post-layout evaluations are presented in this paper. This paper shows that the proposed preprocessor achieves a throughput of 40.7 kMatrices per second for a complexity of 73.3 kGE. Compared with prior work, the proposed preprocessor achieves the highest processing throughput and best efficiency.

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Section: B Related Workmentioning

confidence: 99%

Section: B Comparison With Prior Designsmentioning

confidence: 99%

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Configurable Independent Component Analysis Preprocessing Accelerator

Lu¹,

Shen²,

Fouda³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…So, it is difficult to bring the required hardware efficiency even with the AJM. According to [28] the AJM is superior to the EJM in terms of efficiency (eigenvalues produced per second per unit chip area) but both methods are still in use [23], [38], [39], [40] for implementing FastICA on FPGAs or ASICs. In the AJM, are approximated to the closest CORDIC iteration values, that is why the existing two methods are considered as CORDIC-based methods.…”

Section: F Problem Formulationmentioning

confidence: 99%

“…Using a divider and a square root circuit to perform all the operations of FastICA can save hardware resources but speed performance cannot be achieved in such cases as in [12]. In [50] a System on Chip (SoC, programable logic along with an Arm processor) is used for [51] (2011) [33] (2014) [10] (2015) [53] (2015) [11] (2015) [52] (2016) [12] (2018) [50] (2019) [54] (2019) [39] (2020) [20] This Work implementing these operations. In [51] no hardware utilization or power consumption is reported so we cannot have a fair comparison.…”

Section: Comparing Design Parametersmentioning

confidence: 99%

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

et al. 2021

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Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A Field programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJMbased FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA.

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Catalogic Systematic Literature Review of Hardware-Accelerated Neurodiagnostic Systems

Mittal

Prince

2022

Biomedical Signals Based Computer-Aided Diagnosis for Neurological Disorders

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Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Cited by 11 publications

References 19 publications

Configurable Independent Component Analysis Preprocessing Accelerator

Configurable Independent Component Analysis Preprocessing Accelerator

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

Catalogic Systematic Literature Review of Hardware-Accelerated Neurodiagnostic Systems

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