Hardware Sharing for Channel Interleavers in 5G NR Standard

Abstract

Interleaver module is an important part of modern mobile communication system. It plays an important role in reducing bit error rate and improving transmission efficiency over fading channels. In 5G NR (5th Generation New Radio) standards, LDPC (low-density parity-check) and polar channel codes are employed for data channels and control channels, respectively. If multiple interleavers are implemented separately for them, the cost increases significantly. To address this issue, a hardware multiplexing scheme for channel interleavers based on LDPC and polar codes is proposed in this paper. Firstly, the formulas for the processes of the control channel interleaving and data channel interleaving are derived with respect to 5G NR standard. Then, the hardware implementation structures of the two interleavers are given. Subsequently, hardware reuse is proposed by sharing the similar or identical parts between the two hardware structures. Simulation results verify the correctness of our proposed scheme and demonstrate that it can realize the hardware sharing of the two kinds of channel interleavers to reduce the cost of silicon.

A reduced complexity rate-matching and channel interleaver/de-interleaver for 5G NR

“…Table 2 illustrates a comprehensive comparison of device utilization between the existing architectures and the proposed SRC synthesized for maximum value of E for both polar codes and LDPC code. To maintain a fair evaluation, a multiplexed hardware of channel interleaver designed for 5 G, as presented in [30], and interleaver architecture for WiMAX, WLAN and LTE [19,23,24], serves as a reference. The architecture in [30] is synthesized using the Xilinx ISE design suite on Virtex-7 FPGA, and its resource utilization is contrasted with that of the proposed SRC.…”

“…The memory of the proposed interleaver is configured with a maximum size limit to encompass both data and control channel data bits. Specifically, the highest interleaver size for the polar codes in control channel is determined to be 8192 bits [30]. For LDPC, where N represents the code length, N = 66Z c for BG1, N = 50Z c for BG2, and the maximum lifting size Z c is set at 384.…”

“…Efficient algorithms have been developed to read interleaved bits directly from rate matching buffers, reducing latency, and eliminating the need for separate buffers [29]. Another study introduces a hardware multiplexed channel interleaver architecture for 5G NR based on 3GPP standards [30]. However, despite these advancements, a gap exists in the implementation of an integrated architecture for channel interleaving in 5G NR.…”

“…The SRC is created on a simple algorithm resulting from the 3GPP Release 15 (R15) for 5G NR [32]. Complex formula derivation for data and control interleaver to aid hardware sharing is avoided in comparison with the existing hardware multiplexed architecture [30].…”

Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

“…For LDPC codes, a higher-order bit interleave scheme is proposed, which reduces the bit error rate (BER) of the system compared with traditional maximum likelihood decoding [15]. We have previously proposed an interleave multiplexing scheme of LDPC code and polar code that multiplexes computing units with the same functions, improving the flexibility of the 5G link and saving silicon area [16].…”