Hardware simulation for exponential blind equal throughput algorithm using system generator

Abstract

Scheduling mechanism is the process of allocating radio resources to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution base station, Evolved Node B. Normally, most of the proposed algorithms are not focusing on handling the real-time and non-real-time traffics simultaneously. Thus, UE with bad channel quality may starve due to no resources allocated for quite a long time. To solve the problems, Exponential Blind Equal Throughput (EXP-BET) algorithm is proposed. User with the highest priority metrics is allocated the resources firstly which is calculated using the EXP-BET metric equation. This study investigates the implementation of the EXP-BET scheduling algorithm on the FPGA platform. The metric equation of the EXP-BET is modelled and simulated using System Generator. This design has utilized only 10% of available resources on FPGA. Fixed numbers are used for all the input to the scheduler. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm. The output from the hardware co-simulation showed that the metric values of EXP-BET produce similar results to the Simulink environment. Thus, the algorithm is ready for prototyping and Virtex-6 FPGA is chosen as the platform.

Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation

“…Recently, Xilinx System Generator (XSG) for Digital Signal Processor (DSP) applications is a library integrated inside Simulink program permits to design, simulate, and produce a VHDL code for a digital hardware model of different computational and communication systems [12] of XSG is the simplicity of generating a VHDL code for complex hardware systems and provide the required synchronization between different parts of the model in the graphical user interface (GUI), which consider as a difficult task in complex digital systems [13][14]. Another advantage provided by XSG is hardware co-simulation in which a hardware model implemented into the FPGA board can be simulated in the MATLAB program environment.…”