Hardware/Software Codesign for Embedded Implementation of Neural Networks

Torres-Huitzil, César; Girau, Bernard; Gauffriau, Adrien

doi:10.1007/978-3-540-71431-6_16

Cited by 11 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The approach discussed here involves a hardware-software co-design to optimize on performance and programmability [4], [5] [7]. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired.…”

Section: The Proposed Approachmentioning

confidence: 99%

Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing

Ravi

Moorthy

Vidya³

et al. 2011

AMM

View full text Add to dashboard Cite

Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.

show abstract

Section: The Proposed Approachmentioning

confidence: 99%

Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing

Ravi

Moorthy

Vidya³

et al. 2011

AMM

View full text Add to dashboard Cite

show abstract

“…Regarding macro-architectural exploration Farrugia et al [Far+07] presented a dataflow based Architecture Algorithm Adequation (AAA) methodology in order to find the best compromise between the processing power and functionality requirement of each processor element (PE). Torres et al [THGG07] developed a software platform called NNetWARE-Builder, which takes as inputs graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools.…”

Section: Related Workmentioning

confidence: 99%

Distributed artificial neural network architecture over wireless sensor network

Ortega¹

View full text Add to dashboard Cite

show abstract

Implementation of Central Pattern Generator in an FPGA-Based Embedded System

Torres-Huitzil¹,

Girau

Artificial Neural Networks - ICANN 2008

Self Cite

View full text Add to dashboard Cite

This paper proposes an embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by biological neural networks called Central Pattern Generators (CPGs) found in animal nervous system. The proposed system contains a custom digital module, attached to an embedded processor, that mimics the functionality and organization of the fundamental Amari-Hopfield CPG. In order to reduce the CPG hardware integration complexity as well as to provide flexibility, an embedded linux operating system running on a processor is used to deal with the CPG interfacing in a high level transparent way for application development. The system is implemented on a Field Programmable Gate Array (FPGA) device providing a compact, flexible and expandable solution for generating periodic rhythmic patterns in robot control applications. Results show that the obtained waveforms from the FPGA implementation agree with software simulations and preserve the easiness of CPG parameter setting for adaptive behavior.

show abstract

Hardware/Software Codesign for Embedded Implementation of Neural Networks

Cited by 11 publications

References 14 publications

Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing

Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing

Distributed artificial neural network architecture over wireless sensor network

Implementation of Central Pattern Generator in an FPGA-Based Embedded System

Contact Info

Product

Resources

About