Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Jeong, Byungil; Yoo, Sungjoo; Lee, Sung Hyun; Choi, Ki‐Young

doi:10.1145/368434.368598

Cited by 28 publications

(22 citation statements)

References 4 publications

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“…We focus on integrating key architectural constraints and placement considerations into the scheduling formulation for the more realistic scenario of varying task sizes. Our work is most closely related to [6] and [7]. Mei et al…”

Section: Related Workmentioning

confidence: 68%

“…However, their approach does not consider prefetch or the single reconfiguration controller bottleneck. Jeong et al [7] present an exact algorithm (ILP) and a KLFM-based approach. Their ILP considers prefetch and the single reconfiguration controller bottleneck-however, while scheduling, they do not consider the critical issue of physical task placement.…”

Section: Related Workmentioning

confidence: 99%

“…In Table1, T opt denotes the schedule length obtained with our ILP formulation, T area opt denotes the schedule length obtained from an exact formulation that considers available HW area instead of exact task placement (i.e, placement-unaware) [7]. As Table1 shows, in some cases, T area opt is shorter than T opt , but in these cases the schedules were physically unrealizable with exact placement, while our ILP (T opt ) guarantees placement through correct by construction.…”

Section: Ms ---------------------------mentioning

confidence: 99%

“…However, our target system architecture imposes strict linear placement constraints. Under such constraints, even an optimal schedule generated without considering the exact physical location of the task [7], may be physically unrealizable because of placement infeasibility.…”

Section: Introductionmentioning

confidence: 99%

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Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Banerjee

Bozorgzadeh

Dutt

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placementuanaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable-task graphs with hundreds of nodes are processed in a couple of minutes.

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Section: Related Workmentioning

confidence: 68%

Section: Related Workmentioning

confidence: 99%

Section: Ms ---------------------------mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Banerjee

Bozorgzadeh

Dutt

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…The authors of [10] present HW/SW co-synthesis for run-time reconfigurable systems, relying on an exact algorithm (ILP) and a KLFM-based approach. Their ILP considers the single reconfiguration controller bottleneck and reconfiguration time hiding.…”

Section: Related Workmentioning

confidence: 99%

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

Dittmann

Götz

Rettberg

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required. Such methods must respect the whole range of functionality of the reconfigurable fabrics. In particular, the heterogeneity and reconfiguration delay of modern FPGAs are important details. Comprehensive methods to exploit these characteristics within the integrated design of embedded systems are still not available. In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration. The methodology bases on profound concepts, and expands known notations and model techniques.

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