Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

Abstract

When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required. Such methods must respect the whole range of functionality of the reconfigurable fabrics. In particular, the heterogeneity and reconfiguration delay of modern FPGAs are important details. Comprehensive methods to exploit these characteristics within the integrated design of embedded systems are still not available. In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration. The methodology bases on profound concepts, and expands known notations and model techniques.

Mapping and scheduling with task clustering for heterogeneous computing systems

“…• An analysis of different neighborhood functions and two heuristic search techniques, simulated annealing [11] list scheduling FFT scheduling based on depth of task and number of successors, for MONTIUM architecture [3] list scheduling navigation system shortest job first [9] iteratively moving random graph iteratively move critical task from software processor to hardware processor [5] [12] genetic algorithm random graphs address mapping only simulated annealing [6] [7] [13] heuristic search + random graphs, FFT, JPEG divide mapping/scheduling into two steps lish scheduling [10] [14] heuristic search mean value analysis, FFT address software processor only mapping + scheduling [4] integer linear programming filtering for VLIW architecture only this work heuristic search 40 random graphs clustering + mapping + scheduling 5 applications and tabu search.…”